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order this document by MC68HC708AS48/d rev. 4.0 non-disclosure agreement required MC68HC708AS48 advance information this document contains information on a new product. specifications and information herein are subject to change without notice. hc08 hc08 hc08
non-disclosure agreement required advance information advance information MC68HC708AS48 rev. 4.0 2 motorola motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. ?motorola, inc., 1999
MC68HC708AS48 rev. 4.0 advance information motorola list of sections 3 advance information MC68HC708AS48 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 27 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 3. random-access memory (ram) . . . . . . . . . 55 section 4. erasable programmable read-only memory (eprom/otprom) . . . . . . . . . . . . . . . . . 57 section 5. configuration register (config) . . . . . . . . . 63 section 6. electrically erasable programmable rom (eeprom). . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 7. central processor unit (cpu) . . . . . . . . . . . . 79 section 8. clock generator module (cgm) . . . . . . . . . 97 section 9. system integration module (sim) . . . . . . . . 125 section 10. low-voltage inhibit (lvi). . . . . . . . . . . . . . 149 section 11. break module (break) . . . . . . . . . . . . . . . . 155 section 12. monitor rom (mon) . . . . . . . . . . . . . . . . . 161 section 13. computer operating properly (cop) . . . 171 section 14. external interrupt . . . . . . . . . . . . . . . . . . . . 177 section 15. input/output (i/o) ports . . . . . . . . . . . . . . 185 section 16. timer interface (tim) . . . . . . . . . . . . . . . . . 211 section 17. serial communications interface (sci) . . 243
list of sections advance information MC68HC708AS48 rev. 4.0 4 list of sections motorola section 18. serial peripheral interface (spi) . . . . . . . . 283 section 19. analog-to-digital converter (adc) . . . . . 317 section 20. byte data link controllerCdigital (bdlcCd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 section 21. electrical specifications . . . . . . . . . . . . . . 377 section 22. mechanical specifications . . . . . . . . . . . . 391 section 23. ordering information . . . . . . . . . . . . . . . . . 393
MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 5 advance information MC68HC708AS48 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.5.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . .33 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . .34 1.5.3 external reset pin ( rst) . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.5.4 external interrupt pin ( irq/v pp ) . . . . . . . . . . . . . . . . . . . . .34 1.5.5 analog power supply pin (v dda /v ddaref ). . . . . . . . . . . . .34 1.5.6 analog ground pin (v ssa /v refl ) . . . . . . . . . . . . . . . . . . . .34 1.5.7 external filter capacitor pin (cgmxfc). . . . . . . . . . . . . . .35 1.5.8 port a input/output (i/o) pins (pta7 C pta0) . . . . . . . . . . .35 1.5.9 port b i/o pins (ptb7/atd7Cptb0/atd0). . . . . . . . . . . . .35 1.5.10 port c i/o pins (ptc5Cptc0). . . . . . . . . . . . . . . . . . . . . . .35 1.5.11 port d i/o pins (ptd7/atd15Cptd0/atd8) . . . . . . . . . . .35 1.5.12 port e i/o pins (pte7/spsckCpte0/txd) . . . . . . . . . . . .36 1.5.13 port f i/o pins (ptf4Cptf0/tch2) . . . . . . . . . . . . . . . . . .36 1.5.14 port g i/o pins (ptg2Cptg0) . . . . . . . . . . . . . . . . . . . . . .36 1.5.15 j1850 transmit pin digital (bdtxd) . . . . . . . . . . . . . . . . . .36 1.5.16 j1850 receive pin digital (bdrxd) . . . . . . . . . . . . . . . . . .36 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.3 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
table of contents table of contents MC68HC708AS48 rev. 4.0 6 table of contents motorola section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 section 4. erasable programmable read-only memory (eprom/otprom) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.4 eprom/otprom control register. . . . . . . . . . . . . . . . . . . . .59 4.5 eprom/otprom programming . . . . . . . . . . . . . . . . . . . . . . .60 4.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 section 5. configuration register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 section 6. electrically erasable programmable rom (eeprom) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.4.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.4.2 eeprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.4.3 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . .72 6.4.4 eeprom redundant mode . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.6 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . .74
table of contents MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 7 6.4.7 eeprom non-volatile register and eeprom array configuration register . . . . . . . . . . . . .76 6.4.8 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.8.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.8.2 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 section 7. central processor unit (cpu) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 7.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 7.4.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .87 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .87 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.4.1 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.4.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . .101 8.4.2.1 circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . .103 8.4.2.3 manual and automatic pll bandwidth modes . . . . . . .103 8.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . .107 8.4.3 base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . .107 8.4.4 cgm external connections. . . . . . . . . . . . . . . . . . . . . . . .108
table of contents table of contents MC68HC708AS48 rev. 4.0 8 table of contents motorola 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 8.5.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . .109 8.5.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . .109 8.5.3 external filter capacitor pin (cgmxfc). . . . . . . . . . . . . .109 8.5.4 analog power pin (v dda /v ddaref ). . . . . . . . . . . . . . . . . .110 8.5.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . .110 8.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . .110 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . .110 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . .110 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . .114 8.6.3 pll programming register . . . . . . . . . . . . . . . . . . . . . . . .116 8.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.9 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . .119 8.10 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . .119 8.10.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . .119 8.10.2 parametric influences on reaction time . . . . . . . . . . . . .121 8.10.3 choosing a filter capacitor. . . . . . . . . . . . . . . . . . . . . . . .122 8.10.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . .123 section 9. system integration module (sim) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . .129 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.3.2 clock startup from por or lvi reset. . . . . . . . . . . . . . . .129 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . .130 9.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . .130 9.4.1 external pin reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.4.2 active resets from internal sources . . . . . . . . . . . . . . . . .132 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 9.4.2.2 computer operating properly (cop) reset . . . . . . . . .134 9.4.2.3 illegal opcode reset. . . . . . . . . . . . . . . . . . . . . . . . . . .134
table of contents MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 9 9.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . .134 9.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . .134 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 9.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . .135 9.5.2 sim counter during stop mode recovery . . . . . . . . . . . .135 9.5.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . .135 9.6 program exception control. . . . . . . . . . . . . . . . . . . . . . . . . . .136 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .138 9.6.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.6.3 break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.6.4 status flag protection in break mode. . . . . . . . . . . . . . . .140 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.8.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . .144 9.8.2 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.8.3 sim break flag control register. . . . . . . . . . . . . . . . . . . .147 section 10. low-voltage inhibit (lvi) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 10.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 10.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
table of contents table of contents MC68HC708AS48 rev. 4.0 10 table of contents motorola section 11. break module (break) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 11.4.1 flag protection during break interrupts . . . . . . . . . . . . . .157 11.4.2 cpu during break interrupts. . . . . . . . . . . . . . . . . . . . . . .158 11.4.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . .158 11.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . .158 11.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 11.5.1 break status and control register . . . . . . . . . . . . . . . . . .159 11.5.2 break address registers. . . . . . . . . . . . . . . . . . . . . . . . . .160 11.6 wait or stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 section 12. monitor rom (mon) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 12.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . .164 12.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 12.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 12.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 12.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 12.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 section 13. computer operating properly (cop) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 13.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.1 cgmxclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.4 internal reset resources . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
table of contents MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 11 13.4.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.7 copl (cop long timeout) . . . . . . . . . . . . . . . . . . . . . . .175 13.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.9 cop module during break interrupts . . . . . . . . . . . . . . . . . . .176 section 14. external interrupt 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 14.5 irq/v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 14.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . .182 14.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . .182 section 15. input/output (i/o) ports 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 15.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 15.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 15.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . .189 15.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 15.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 15.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . .192 15.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 15.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 15.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . .195 15.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 15.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 15.6.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . .199
table of contents table of contents MC68HC708AS48 rev. 4.0 12 table of contents motorola 15.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 15.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 15.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . .203 15.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 15.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 15.8.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . .206 15.9 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 15.9.1 port g data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 15.9.2 data direction register g . . . . . . . . . . . . . . . . . . . . . . . . .209 section 16. timer interface (tim) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16.4.2 input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 16.4.3.1 unbuffered output compare. . . . . . . . . . . . . . . . . . . . .218 16.4.3.2 buffered output compare. . . . . . . . . . . . . . . . . . . . . . .219 16.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . .220 16.4.4.1 unbuffered pwm signal generation. . . . . . . . . . . . . . .221 16.4.4.2 buffered pwm signal generation. . . . . . . . . . . . . . . . .222 16.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 16.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 16.7 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .226 16.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16.8.1 tim clock pin (ptd6/atd14/tclk) . . . . . . . . . . . . . . . . .227 16.8.2 tim channel i/o pins (ptf3/tch5Cptf0/tch2, pte3/tch1Cpte2/tch0) . . . . . . . . . . . . . . . . . . . . . .227 16.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 16.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . .228 16.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . .231 16.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . .232
table of contents MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 13 16.9.4 tim channel status and control registers. . . . . . . . . . . .233 16.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . .238 section 17. serial communications interface (sci) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 17.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.4.3 character length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.4.4 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . .249 17.4.5 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 17.4.6 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 17.4.7 inversion of transmitted output . . . . . . . . . . . . . . . . . . . .253 17.4.8 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 17.4.9 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 17.4.10 character length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 17.4.11 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 17.4.12 data sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 17.4.13 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 17.4.14 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 17.5 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 17.5.1 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 17.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .263 17.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 17.8.1 pte0/txd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . .264 17.8.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . .264 17.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 17.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .265 17.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .271 17.9.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 17.9.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
table of contents table of contents MC68HC708AS48 rev. 4.0 14 table of contents motorola 17.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 17.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . .280 section 18. serial peripheral interface (spi) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 18.4 pin name and register name conventions . . . . . . . . . . . . . .285 18.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 18.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 18.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 18.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 18.6.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . .290 18.6.2 transmission format when cpha = 0 . . . . . . . . . . . . . . .291 18.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . .292 18.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . .294 18.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 18.7.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 18.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 18.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.9 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . .301 18.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 18.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .305 18.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 18.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . .306 18.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . .307 18.13.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 18.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 18.13.5 v ss (clock ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 18.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 18.14.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 18.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . .312 18.14.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
table of contents MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 15 section 19. analog-to-digital converter (adc) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 19.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 19.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 19.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 19.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .321 19.4.5 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . .321 19.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 19.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.7.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . .322 19.7.2 adc analog ground pin (v ssa )/adc voltage reference low pin (v refl ). . . . . . . . . . . . . . .323 19.7.3 adc voltage in (adcvin). . . . . . . . . . . . . . . . . . . . . . . . .323 19.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 19.8.1 adc status and control register . . . . . . . . . . . . . . . . . . .324 19.8.2 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 19.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . .327 section 20. byte data link controllerCdigital (bdlcCd) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 20.4.1 bdlc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . .334 20.4.1.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 20.4.1.2 reset mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 20.4.1.3 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 20.4.1.4 bdlc wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 20.4.1.5 bdlc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
table of contents table of contents MC68HC708AS48 rev. 4.0 16 table of contents motorola 20.4.1.6 digital loopback mode . . . . . . . . . . . . . . . . . . . . . . . . .336 20.4.1.7 analog loopback mode . . . . . . . . . . . . . . . . . . . . . . . .336 20.5 bdlc mux interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 20.5.1 rx digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 20.5.1.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 20.5.1.2 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 20.5.2 j1850 frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 20.5.3 j1850 vpw symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 20.5.4 j1850 vpw valid/invalid bits and symbols . . . . . . . . . . .346 20.5.5 message arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 20.6 bdlc protocol handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 20.6.1 protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 20.6.2 rx and tx shift registers . . . . . . . . . . . . . . . . . . . . . . . . .353 20.6.3 rx and tx shadow registers . . . . . . . . . . . . . . . . . . . . . .354 20.6.4 digital loopback multiplexer . . . . . . . . . . . . . . . . . . . . . . .354 20.6.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.6.5.1 4x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.6.5.2 receiving a message in block mode . . . . . . . . . . . . . .355 20.6.5.3 transmitting a message in block mode . . . . . . . . . . . .355 20.6.5.4 j1850 bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.6.5.5 summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 20.7 bdlc cpu interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20.7.1 bdlc analog and roundtrip delay. . . . . . . . . . . . . . . . . .358 20.7.2 bdlc control register 1. . . . . . . . . . . . . . . . . . . . . . . . . .360 20.7.3 bdlc control register 2. . . . . . . . . . . . . . . . . . . . . . . . . .363 20.7.4 bdlc state vector register . . . . . . . . . . . . . . . . . . . . . . .371 20.7.5 bdlc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 section 21. electrical specifications 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 21.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 21.3 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . .379 21.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 21.5 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . .380
table of contents MC68HC708AS48 rev. 4.0 table of contents motorola table of contents 17 21.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 21.7 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.8 5.0 vdc 10% serial peripheral interface (spi) timing . . . . .383 21.9 cgm operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .386 21.10 cgm component information. . . . . . . . . . . . . . . . . . . . . . . . .386 21.11 cgm acquisition/lock time information . . . . . . . . . . . . . . . .387 21.12 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . .388 21.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 21.14 bdlc transmitter vpw symbol timings . . . . . . . . . . . . . . . .388 21.15 bdlc receiver vpw symbol timings . . . . . . . . . . . . . . . . . .389 21.16 bdlc transmitter dc electrical characteristics . . . . . . . . . .390 21.17 bdlc receiver dc electrical characteristics . . . . . . . . . . . .390 section 22. mechanical specifications 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 22.3 52-pin plastic leaded chip carrier package (case 778) . . . . . . . . . . . . . . . . . . . . . . .392 section 23. ordering information 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 23.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
table of contents table of contents MC68HC708AS48 rev. 4.0 18 table of contents motorola
MC68HC708AS48 rev. 4.0 advance information motorola list of figures 19 non-disclosure agreement required advance information MC68HC708AS48 list of figures figure title page 1-1 mcu block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1-2 52-pin plcc assignments (top view) . . . . . . . . . . . . . . . .31 1-3 64-pin qfp assignments (top view). . . . . . . . . . . . . . . . . .32 1-4 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2-2 control, status, and data registers. . . . . . . . . . . . . . . . . . .45 4-1 eprom/otprom control register (epmcr) . . . . . . . . . .59 5-1 configuration register (config) . . . . . . . . . . . . . . . . . . . .64 6-1 eeprom control register (eecr) . . . . . . . . . . . . . . . . . . .74 6-2 eeprom array control register (eeacr) . . . . . . . . . . . . .76 6-3 eeprom non-volatile register (eenvr) . . . . . . . . . . . . . .76 7-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7-3 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 7-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . .85 8-1 cgm block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8-2 cgm i/o register summary . . . . . . . . . . . . . . . . . . . . . . .101 8-3 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . .109 8-4 cgm i/o register summary . . . . . . . . . . . . . . . . . . . . . . .111 8-5 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . .112 8-6 pll bandwidth control register (pbwc) . . . . . . . . . . . . .114 8-7 pll programming register (ppg) . . . . . . . . . . . . . . . . . . .116
non-disclosure agreement required list of figures advance information MC68HC708AS48 rev. 4.0 20 list of figures motorola figure title page 9-1 sim block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9-2 sim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . .128 9-3 cgm clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 9-6 sources of internal reset. . . . . . . . . . . . . . . . . . . . . . . . . .132 9-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 9-8 interrupt entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 9-9 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9-10 interrupt recovery timing . . . . . . . . . . . . . . . . . . . . . . . . .138 9-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . .139 9-12 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9-13 wait recovery from interrupt or break . . . . . . . . . . . . . . . .142 9-14 wait recovery from internal reset . . . . . . . . . . . . . . . . . .142 9-15 stop mode entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . .143 9-16 stop mode recovery from interrupt or break. . . . . . . . . . .143 9-17 sim break status register (sbsr) . . . . . . . . . . . . . . . . . .144 9-18 sim reset status register (srsr) . . . . . . . . . . . . . . . . . .146 9-19 sim break flag control register (sbfcr) . . . . . . . . . . . .147 10-1 lvi module block diagram. . . . . . . . . . . . . . . . . . . . . . . . .150 10-2 lvi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . .151 10-3 lvi status register (lvisr). . . . . . . . . . . . . . . . . . . . . . . .152 11-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . .157 11-2 break i/o register summary . . . . . . . . . . . . . . . . . . . . . . .157 11-3 break status and control register (brkscr) . . . . . . . . .159 11-4 break address register (brkh) . . . . . . . . . . . . . . . . . . . .160 11-5 break address register (brkl). . . . . . . . . . . . . . . . . . . . .160 12-1 monitor mode circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 12-2 monitor data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 12-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . .165 12-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 12-5 break transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 13-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 13-2 cop i/o register summary . . . . . . . . . . . . . . . . . . . . . . . .172
list of figures MC68HC708AS48 rev. 4.0 advance information motorola list of figures 21 non-disclosure agreement required figure title page 13-3 cop control register (copctl). . . . . . . . . . . . . . . . . . . .175 14-1 irq block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 14-2 irq i/o register summary . . . . . . . . . . . . . . . . . . . . . . . .179 14-3 irq interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .180 14-4 irq status and control register (iscr) . . . . . . . . . . . . . .183 15-1 i/o port register summary . . . . . . . . . . . . . . . . . . . . . . . .186 15-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . .188 15-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . .189 15-4 port a i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 15-5 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . .191 15-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . .192 15-7 port b i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 15-8 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . .194 15-9 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . .195 15-10 port c i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 15-11 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . .197 15-12 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . .199 15-13 port d i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 15-14 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . .201 15-15 data direction register e (ddre) . . . . . . . . . . . . . . . . . . .203 15-16 port e i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 15-17 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . .205 15-18 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . .206 15-19 port f i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 15-20 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . .208 15-21 data direction register g (ddrg) . . . . . . . . . . . . . . . . . .209 15-22 port g i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 16-1 tim block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 16-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . .214 16-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . .220 16-4 tim status and control register (tsc) . . . . . . . . . . . . . . .229 16-5 tim counter registers (tcnth and tcntl) . . . . . . . . . .231 16-6 tim counter modulo registers (tmodh and tmodl) . . . . . . . . . . . . . . . . . . . . . . . . .232
non-disclosure agreement required list of figures advance information MC68HC708AS48 rev. 4.0 22 list of figures motorola figure title page 16-7 tim channel status and control registers (tsc0Ctsc5) . . . . . . . . . . . . . .233 16-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 16-9 tim channel registers (tch0h/lCtch3h/l) . . . . . . . . . .239 17-1 sci module block diagram . . . . . . . . . . . . . . . . . . . . . . . .246 17-2 sci i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . .247 17-3 sci data formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17-4 sci transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 17-5 transmitter i/o register summary. . . . . . . . . . . . . . . . . . .251 17-6 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . .255 17-7 sci receiver i/o register summary . . . . . . . . . . . . . . . . .256 17-8 receiver data sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .258 17-9 sci control register 1 (scc1) . . . . . . . . . . . . . . . . . . . . .266 17-10 sci control register 2 (scc2) . . . . . . . . . . . . . . . . . . . . .269 17-11 sci control register 3 (scc3) . . . . . . . . . . . . . . . . . . . . .272 17-12 sci status register 1 (scs1) . . . . . . . . . . . . . . . . . . . . . .274 17-13 flag clearing sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .277 17-14 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . .278 17-15 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . .279 17-16 sci baud rate register 1 (scbr) . . . . . . . . . . . . . . . . . .280 18-1 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . .286 18-2 spi module block diagram . . . . . . . . . . . . . . . . . . . . . . . .287 18-3 full-duplex master-slave connections . . . . . . . . . . . . . . .288 18-4 transmission format (cpha = 0) . . . . . . . . . . . . . . . . . . .291 18-5 cpha/ ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 18-6 transmission format (cpha = 1) . . . . . . . . . . . . . . . . . . .293 18-7 transmission start delay (master) . . . . . . . . . . . . . . . . . . .295 18-8 missed read of overflow condition . . . . . . . . . . . . . . . . . .297 18-9 clearing sprf when ovrf interrupt is not enabled . . . .298 18-10 spi interrupt request generation . . . . . . . . . . . . . . . . . . .301 18-11 sprf/spte cpu interrupt timing. . . . . . . . . . . . . . . . . . .302 18-12 cpha/ ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 18-13 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . .310 18-14 spi status and control register (spscr). . . . . . . . . . . . .313 18-15 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . .316
list of figures MC68HC708AS48 rev. 4.0 advance information motorola list of figures 23 non-disclosure agreement required figure title page 19-1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 19-2 adc status and control register (adscr). . . . . . . . . . . .324 19-3 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . .327 19-4 adc input clock register (adiclk) . . . . . . . . . . . . . . . . .327 20-1 bdlc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 20-2 bdlc input/output (i/o) register summary . . . . . . . . . . .333 20-3 bdlc operating modes state diagram . . . . . . . . . . . . . . .334 20-4 bdlc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 20-5 bdlc rx digital filter block diagram . . . . . . . . . . . . . . . .338 20-6 j1850 bus message format (vpw) . . . . . . . . . . . . . . . . . .340 20-7 j1850 vpw symbols with nominal symbol times . . . . . .344 20-8 j1850 vpw received passive symbol times . . . . . . . . . .347 20-9 j1850 vpw received passive eof and ifs symbol times . . . . . . . . . . . . . . . . . . . . .348 20-10 j1850 vpw received active symbol times . . . . . . . . . . .349 20-11 j1850 vpw received break symbol times . . . . . . . . . .350 20-12 j1850 vpw bitwise arbitrations. . . . . . . . . . . . . . . . . . . . .351 20-13 bdlc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 20-14 bdlc protocol handler outline . . . . . . . . . . . . . . . . . . . . .353 20-15 bdlc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20-16 bdlc analog and roundtrip delay register (bard) . . . .358 20-17 bdlc control register 1 (bcr1) . . . . . . . . . . . . . . . . . . . .360 20-18 bdlc control register 2 (bcr2) . . . . . . . . . . . . . . . . . . . .363 20-19 types of in-frame response (ifr) . . . . . . . . . . . . . . . . . .367 20-20 bdlc state vector register (bsvr) . . . . . . . . . . . . . . . . .371 20-21 bdlc data register (bdr) . . . . . . . . . . . . . . . . . . . . . . . .373 21-1 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384 21-2 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 21-3 bdlc variable pulse width modulation (vpw) symbol timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
non-disclosure agreement required list of figures advance information MC68HC708AS48 rev. 4.0 24 list of figures motorola
MC68HC708AS48 rev. 4.0 list of tables motorola list of tables 25 advance information MC68HC708AS48 list of tables table title page 1-1 external pins summary .........................................................37 1-2 clock source summary..........................................................39 2-1 vector addresses ..................................................................53 6-1 eeprom program/erase cycling reduction.........................71 6-2 eeprom array address blocks.............................................72 6-3 eeprom program/erase mode select..................................75 7-1 instruction set summary ........................................................88 7-2 opcode map ...........................................................................96 8-1 vco frequency multiplier (n) selection...............................116 9-1 signal name conventions ....................................................128 9-2 pin bit set timing ................................................................131 10-1 lviout bit indication ...........................................................152 12-1 mode selection ....................................................................164 12-2 mode differences .................................................................165 12-3 read (read memory) command ........................................167 12-4 write (write memory) command.......................................168 12-5 iread (indexed read) command .......................................168 12-6 iwrite (indexed write) command......................................169 12-7 readsp (read stack pointer) command...........................169 12-8 run (run user program) command...................................170 12-9 monitor baud rate selection................................................170
list of tables list of tables MC68HC708AS48 rev. 4.0 26 list of tables motorola table title page 15-1 port a pin functions.............................................................190 15-2 port b pin functions.............................................................193 15-3 port c pin functions.............................................................196 15-4 port d pin functions.............................................................200 15-5 port e pin functions.............................................................204 15-6 port f pin functions .............................................................207 15-7 port g pin functions ............................................................210 16-1 prescaler selection...............................................................230 16-2 mode, edge, and level selection.........................................237 17-1 start bit verification ..............................................................259 17-2 data bit recovery.................................................................259 17-3 stop bit recovery.................................................................260 17-4 character format selection..................................................268 17-5 sci baud rate prescaling....................................................280 17-6 sci baud rate selection......................................................281 17-7 sci baud rate selection examples .....................................282 18-1 pin name conventions.........................................................285 18-2 i/o register addresses ........................................................285 18-3 spi interrupts........................................................................300 18-4 spi configuration .................................................................309 18-5 spi master baud rate selection ..........................................315 19-1 mux channel select .............................................................326 19-2 adc clock divide ratio........................................................328 20-1 bdlc j1850 bus error summary.........................................357 20-2 bdlc transceiver delay .....................................................360 20-3 bdlc rate selection............................................................362 20-4 bdlc transmit in-frame response control bit priority encoding............................................366 20-5 bdlc interrupt sources .......................................................371 23-1 mc order numbers ..............................................................393
MC68HC708AS48 rev. 4.0 advance information motorola general description 27 non-disclosure agreement required advance information MC68HC708AS48 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.5.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . .33 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . .34 1.5.3 external reset pin ( rst) . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.5.4 external interrupt pin ( irq/v pp ) . . . . . . . . . . . . . . . . . . . . .34 1.5.5 analog power supply pin (v dda /v ddaref ). . . . . . . . . . . . .34 1.5.6 analog ground pin (v ssa /v refl ) . . . . . . . . . . . . . . . . . . . .34 1.5.7 external filter capacitor pin (cgmxfc). . . . . . . . . . . . . . .35 1.5.8 port a input/output (i/o) pins (pta7 C pta0) . . . . . . . . . . .35 1.5.9 port b i/o pins (ptb7/atd7Cptb0/atd0). . . . . . . . . . . . .35 1.5.10 port c i/o pins (ptc5Cptc0). . . . . . . . . . . . . . . . . . . . . . .35 1.5.11 port d i/o pins (ptd7/atd15Cptd0/atd8) . . . . . . . . . . .35 1.5.12 port e i/o pins (pte7/spsckCpte0/txd) . . . . . . . . . . . .36 1.5.13 port f i/o pins (ptf4Cptf0/tch2) . . . . . . . . . . . . . . . . . .36 1.5.14 port g i/o pins (ptg2Cptg0) . . . . . . . . . . . . . . . . . . . . . .36 1.5.15 j1850 transmit pin digital (bdtxd) . . . . . . . . . . . . . . . . . .36 1.5.16 j1850 receive pin digital (bdrxd) . . . . . . . . . . . . . . . . . .36
non-disclosure agreement required general description advance information MC68HC708AS48 rev. 4.0 28 general description motorola 1.2 introduction the MC68HC708AS48 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the MC68HC708AS48 include: ? high-performance m68hc08 architecture ? fully upward-compatible object code with m6805, m146805, and m68hc05 families ? 8.4-mhz internal bus frequency ? 49,152 bytes of on-chip uv erasable programmable read-only memory (eprom) or one-time programmable read-only memory (otprom) ? on-chip programming firmware for use with host personal computer ? eprom/otprom data security 1 ? 640 bytes of on-chip electrically erasable programmable read-only memory (eeprom) ? 1,536 bytes of on-chip ram ? serial peripheral interface module (spi) ? serial communications interface module (sci) ? 16-bit, 6-channel timer interface module (tim) ? clock generator module (cgm) 1. no security feature is absolutely secure. however, motorolas strategy is to make reading or copying the eprom/otprom difficult for unauthorized users.
general description mcu block diagram MC68HC708AS48 rev. 4.0 advance information motorola general description 29 non-disclosure agreement required ? 8-bit, 15-channel in 52-pin plastic leaded chip carrier (plcc), or 16-channel in 64-pin quad flat pack (qfp) analog-to-digital converter module (adc) ? sae j1850 byte data link controller digital module (bdlc-d) ? system protection features C computer operating properly (cop) with optional reset C low-voltage detection with optional reset C illegal opcode detection with optional reset C illegal address detection with optional reset ? low-power design (fully static with stop and wait modes) ? master reset pin and power-on reset features of the cpu08 include: ? enhanced hc05 programming model ? extensive loop control functions ? 16 addressing modes (eight more than the hc05) ? 16-bit index register and stack pointer ? memory-to-memory data transfers ? fast 8 8 multiply instruction ? fast 16/8 divide instruction ? binary-coded decimal (bcd) instructions ? optimization for controller applications ? c language support 1.4 mcu block diagram figure 1-1 shows the structure of the MC68HC708AS48.
non-disclosure agreement required advance information MC68HC708AS48 rev. 4.0 30 general description motorola general description break module clock generator module system integration module analog-to-digital converter module serial communications interface module serial peripheral interface module timer interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers 62 bytes user eprom 49,152 bytes user ram 1536 bytes monitor rom 224 bytes user eprom vector space 36 bytes irq module ddrd ptd ddre pte ptg ddrg internal bus osc1 osc2 cgmxfc rst irq/v pp v ss v dd v dda /v ddaref v ssa /v refl ptd5/atd13Cptd3/atd11 pte7/spsck pte6/mosi pte5/miso pte4/ ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf4 ptf3/tch5 ptf2/tch4 ptf ddrf (ptg: 64-pin package only) ptg2-ptg0 bdtxd bdrxd power ptd1/atd9Cptd0/atd8 ptd2/atd10 ptf1/tch3 ptf0/tch2 byte data link controller digital module (ptd7/atd15: 64-pin package only) ptd7/atd15 ptd6/atd14/tclk pta ddra ddrb ptb ddrc ptc pta7Cpta0 ptb7/atd7Cptb0/atd0 ptc5Cptc3 (ptc5: 64-pin package only) ptc2/mclk ptc1Cptc0 v refh (ptf4: 64-pin package only) figure 1-1. mcu block diagram user eeprom 640 bytes
general description pin assignments MC68HC708AS48 rev. 4.0 advance information motorola general description 31 non-disclosure agreement required 1.5 pin assignments figure 1-2 shows the 52-pin plcc assignments. figure 1-2. 52-pin plcc assignments (top view) pte5/miso pte4/ ss pte6/mosi pte7/spsck v ss v dd pta0 pta1 pta2 pta3 pta4 pta5 pta6 46 34 ptb4/atd4 ptd3/atd11 ptd2/atd10 ptd1/atd9 ptd0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 bdrxd cgmxfc ptf3/tch5 ptf2/tch4 ptf1/tch3 ptf0/tch2 rst irq/v pp ptc4 bdtxd pte0/txd pte1/rxd pte2/tch0 pte3/tch1 v ssa /v refl v dda /v ddaref v refh ptd6/atd14/tclk ptd5/atd13 ptd4/atd12 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 45 44 43 42 41 40 39 38 37 36 35 7 6 5 4 3 2 1 52 51 50 49 48 47
non-disclosure agreement required general description advance information MC68HC708AS48 rev. 4.0 32 general description motorola figure 1-3 shows the 64-pin qfp assignments. figure 1-3. 64-pin qfp assignments (top view) ptf4 cgmxfc ptb7/atd7 ptf3/tch5 ptf2/tch4 ptf1/tch3 ptf0/tch2 rst irq/v pp ptc4 bdrxd bdtxd nc nc pte0/txd pte1/rxd pte2/tch0 pte3/tch1 nc ptd3/atd11 ptd2/atd10 nc nc ptd1/atd9 ptd0/atd8 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa /v refl v dda /v ddaref v refh ptd7/atd15 ptd6/atd14/tclk ptd5/atd13 ptd4/atd12 nc ptc5 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ ss pte5/miso pte7/spsck v ss v dd ptg0 ptg1 ptg2 pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
general description pin assignments MC68HC708AS48 rev. 4.0 advance information motorola general description 33 non-disclosure agreement required 1.5.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. figure 1-4. power supply bypassing v ss is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (spi). (see section 18. serial peripheral interface (spi) .) note: v ss must be grounded for proper mcu operation. mcu v dd c2 c1 0.1 m f v ss v dd + note: component values shown represent typical applications.
non-disclosure agreement required general description advance information MC68HC708AS48 rev. 4.0 34 general description motorola 1.5.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. (see section 8. clock generator module (cgm) .) 1.5.3 external reset pin ( rst) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. (see section 9. system integration module (sim) for more information.) 1.5.4 external interrupt pin ( irq/v pp ) irq/v pp is an asynchronous external interrupt pin. irq/v pp is also the eprom/otprom programming power pin. (see section 14. external interrupt and section 4. erasable programmable read-only memory (eprom/otprom) .) 1.5.5 analog power supply pin (v dda /v ddaref ) v dda /v ddaref is the power supply pin for the analog portion of the chip. these modules are the analog-to-digital converter (adc) and the clock generator module (cgm). (see section 8. clock generator module (cgm) and section 19. analog-to-digital converter (adc) .) 1.5.6 analog ground pin (v ssa /v refl ) the v ssa /v refl analog ground pin is used only for the ground connections for the analog sections of the circuit and should be decoupled as per the v ss digital ground pin. the analog sections consist of a clock generator module (cgm) and an analog-to-digital converter (adc). v ssa /v refl is also the lower reference supply for the adc. (see section 8. clock generator module (cgm) and section 19. analog-to-digital converter (adc) .)
general description pin assignments MC68HC708AS48 rev. 4.0 advance information motorola general description 35 non-disclosure agreement required 1.5.7 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor connection for the cgm. (see section 8. clock generator module (cgm) .) 1.5.8 port a input/output (i/o) pins (pta7 C pta0) pta7Cpta0 are general-purpose bidirectional i/o port pins. (see section 15. input/output (i/o) ports .) 1.5.9 port b i/o pins (ptb7/atd7Cptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (adc). (see section 19. analog-to-digital converter (adc) and section 15. input/output (i/o) ports .) 1.5.10 port c i/o pins (ptc5Cptc0) ptc5 C ptc3 and ptc1 C ptc0 are general-purpose bidirectional i/o port pins. ptc2/mclk is a special function port that shares its pin with the system clock. ptc5 is only available with the 64-pin qfp package. (see section 15. input/output (i/o) ports .) 1.5.11 port d i/o pins (ptd7/atd15Cptd0/atd8) port d is a 8-bit special function port that shares all of its pins with the analog-to-digital converter module (adc) and one of its pins with the timer interface module (tim). ptd7/atd15 is only available with the 64-pin qfp package. (see section 16. timer interface (tim) , section 19. analog-to-digital converter (adc) , and section 15. input/output (i/o) ports .).
non-disclosure agreement required general description advance information MC68HC708AS48 rev. 4.0 36 general description motorola 1.5.12 port e i/o pins (pte7/spsckCpte0/txd) port e is an 8-bit special function port that shares two of its pins with the timer interface module (tim), four of its pins with the serial peripheral interface module (spi), and two of its pins with the serial communication interface module (sci). (see section 17. serial communications interface (sci) , section 18. serial peripheral interface (spi) , section 16. timer interface (tim) , and section 15. input/output (i/o) ports .) 1.5.13 port f i/o pins (ptf4Cptf0/tch2) port f is a 5-bit special function port that shares four of its pins with the timer interface module (tim). (see section 16. timer interface (tim) and section 15. input/output (i/o) ports .). ptf4 is only available in the 64-pin qfp package. 1.5.14 port g i/o pins (ptg2Cptg0) ptg2-ptg0 are general-purpose bidirectional i/o pins. port g is only available in the 64-pin qfp package. (see section 15. input/output (i/o) ports .) 1.5.15 j1850 transmit pin digital (bdtxd) bdtxd is a serial digital output data physical interface to the j1850. (see section 20. byte data link controllerCdigital (bdlcCd) ). 1.5.16 j1850 receive pin digital (bdrxd) bdrxd is a serial digital input data physical interface from the j1850. (see section 20. byte data link controllerCdigital (bdlcCd) ).
general description pin assignments MC68HC708AS48 rev. 4.0 advance information motorola general description 37 non-disclosure agreement required table 1-1. external pins summary pin name function driver type hysteresis reset state pta7Cpta0 general-purpose i/o dual state no input, hi-z ptb7/atd7C ptb0/atd0 general-purpose i/o adc channel dual state no input, hi-z ptc5Cptc3 general-purpose i/o dual state no input, hi-z ptc2/mclk general-purpose i/o bus clock output dual state no input, hi-z ptc1Cptc0 general-purpose i/o dual state no input, hi-z ptd7/atd15 general-purpose i/o dual state no input, hi-z ptd6/atd14/tclk general-purpose i/o adc channel/timer external input clock dual state no input, hi-z ptd5/atd13C ptd3/atd11 general-purpose i/o adc channel dual state no input, hi-z ptd2/atd10 general-purpose input adc channel n/a no input, hi-z ptd1/atd9- ptd0/atd8 general-purpose i/o adc channel dual state no input, hi-z pte7/spsck general-purpose i/o spi clock dual state open drain yes input, hi-z pte6/mosi general-purpose i/o spi data path dual state open drain yes input, hi-z pte5/miso general-purpose i/o spi data path dual state open drain yes input, hi-z pte4/ ss general-purpose i/o spi slave select dual state yes input, hi-z pte3/tch1 general-purpose i/o timer channel 1 dual state yes input, hi-z pte2/tch0 general-purpose i/o timer channel 0 dual state yes input, hi-z pte1/rxd general-purpose i/o sci receive data dual state yes input, hi-z pte0/txd general-purpose i/o sci transmit data dual state yes input, hi-z ptf4 general-purpose i/o dual state no input, hi-z
non-disclosure agreement required general description advance information MC68HC708AS48 rev. 4.0 38 general description motorola ptf3/tch5 general-purpose i/o timer channel 5 dual state yes input, hi-z ptf2/tch4 general-purpose i/o timer channel 4 dual state yes input, hi-z ptf1/tch3 general-purpose i/o timer channel 3 dual state yes input, hi-z ptf0/tch2 general-purpose i/o timer channel 2 dual state yes input, hi-z ptg2-ptg0 general-purpose i/o dual state yes input, hi-z v dd chip power supply n/a n/a n/a v ss chip ground n/a n/a n/a v dda /v ddaref analog power supply (cgm and adc) n/a n/a n/a v ssa /v refl analog ground a/d reference voltage n/a n/a n/a v refh a/d reference voltage n/a n/a n/a osc1 external clock in n/a n/a input, hi-z osc2 external clock out n/a n/a output cgmxfc pll loop filter cap n/a n/a n/a irq/v pp external interrupt request eprom programming voltage n/a n/a input, hi-z rst reset n/a n/a output low bdrxd bdlc-digital serial input n/a no input, hi-z bdtxd bdlc-digital serial output output no output low table 1-1. external pins summary (continued) pin name function driver type hysteresis reset state
general description pin assignments MC68HC708AS48 rev. 4.0 advance information motorola general description 39 non-disclosure agreement required table 1-2. clock source summary module clock source adc cgmxclk or bus clock bdlc cgmxclk cop cgmxclk cpu bus clock eeprom internal rc oscillator or bus clock spi bus clock/spsck sci cgmxclk tim bus clock or ptd6/atd14/tclk sim cgmout and cgmxclk irq bus clock brk bus clock lvi bus clock cgm osc1 and osc2
non-disclosure agreement required general description advance information MC68HC708AS48 rev. 4.0 40 general description motorola
MC68HC708AS48 rev. 4.0 advance information motorola memory map 41 non-disclosure agreement required advance information MC68HC708AS48 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.3 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: ? 49,152 bytes of user eprom or otprom ? 1,536 bytes of ram ? 640 bytes of eeprom ? 36 bytes of user-defined vectors ? 224 bytes of monitor rom these definitions apply to the memory map representation of reserved and unimplemented locations. ? reserved accessing a reserved location can have unpredictable effects on mcu operation. ? unimplemented accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled.
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 42 memory map motorola $0000 i/o registers 62 bytes ($000b & $000f are reserved) $003f $0040 unimplemented 16 bytes $004f $0050 ram 1,536 bytes $064f $0650 unimplemented 432 bytes $07ff $0800 eeprom 640 bytes $0a7f $0a80 unimplemented 13,184 bytes $3dff $3e00 eprom 49,152 bytes ($ae00-$fdff for 20,480 bytes) $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 reserved $fe05 reserved $fe06 reserved $fe07 eprom control register (epmcr) figure 2-1. memory map
memory map introduction MC68HC708AS48 rev. 4.0 advance information motorola memory map 43 non-disclosure agreement required $fe08 reserved $fe09 reserved $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 reserved 12 bytes $fe1b $fe1c eeprom non-volatile register (eenvr) $fe1d eeprom control register (eecr) $fe1e reserved $fe1f eeprom array configuration register (eeacr) $fe20 monitor rom 224 bytes $feff $ff00 unimplemented 192 bytes $ffbf $ffc0 reserved 28 bytes $ffdb $ffdc interrupt and reset vectors 36 bytes $ffff figure 2-1. memory map (continued)
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 44 memory map motorola 2.3 input/output (i/o) section addresses $0000C$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: ? $fe00, sim break status register, sbsr ? $fe01, sim reset status register, srsr ? $fe03, sim break flag control register, sbfcr ? $fe07, eprom control register, epmcr ? $fe0c and $fe0d, break address registers, brkh and brkl ? $fe0e, break status and control register, brkscr ? $fe0f, lvi status register, lvisr ? $fe1c, eeprom non-volatile register, eenvr ? $fe1d, eeprom control register, eecr ? $fe1f, eeprom array configuration register, eeacr ? $ffff, cop control register, copctl following the registers in figure 2-2 , table 2-1 is a list of vector locations.
memory map input/output (i/o) section MC68HC708AS48 rev. 4.0 advance information motorola memory map 45 non-disclosure agreement required addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 188. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 191. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 194. read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r reset: unaffected by reset $0003 port d data register (ptd) see page 197. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r reset: unaffected by reset $0004 data direction register a (ddra) see page 189. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) see page 192. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) see page 195. read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset: 0 0 0 0 0 0 0 0 $0007 data direction register d (ddrd) see page 199. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 0 ddrd1 ddrd0 write: r reset: 0 0 0 0 0 0 0 0 $0008 port e data register (pte) see page 201. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 1 of 8)
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 46 memory map motorola $0009 port f data register (ptf) see page 205. read: 0 0 0 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r r reset: unaffected by reset $000a port g data register (ptg) see page 208. read: 0 0 0 0 0 ptg2 ptg1 ptg0 write: r r r r r reset: unaffected by reset $000b reserved $000c data direction register e (ddre) see page 203. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 $000d data direction register f (ddrf) see page 206. read: 0 0 0 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r r reset: 0 0 0 0 0 0 0 0 $000e data direction register g (ddrg) see page 209. read: 0 0 0 0 0 ddrg2 ddrg1 ddrg0 write: r r r r r reset: 0 0 0 0 0 0 0 0 $000f reserved $0010 spi control register (spcr) see page 310. read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $0011 spi status and control register (spscr) see page 313. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 $0012 spi data register (spdr) see page 316. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 2 of 8)
memory map input/output (i/o) section MC68HC708AS48 rev. 4.0 advance information motorola memory map 47 non-disclosure agreement required $0013 sci control register 1 (scc1) see page 266. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 269. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 272. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 274. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 278. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 279. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 280. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 $001a irq status and control register (iscr) see page 183. read: 0 0 0 0 irqf 0 imask mode write: r r r r r ack reset: 0 0 0 0 0 0 0 0 $001b reserved $001c pll control register (pctl) see page 112. read: pllie pllf pllon bcs 1111 write: r r r r r reset: 0 0 1 0 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 3 of 8)
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 48 memory map motorola $001d pll bandwidth control register (pbwc) see page 114. read: auto lock a cq xld 0000 write: r r r r r reset: 0 0 0 0 0 0 0 0 $001e pll programming register (ppg) see page 116. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 $001f con?guration register (config) see page 64. read: rr lvirstd lvipwrd ssrec copl stop copd write: r r r r r r reset: unaffected by reset $0020 tim status and control register (tsc) see page 229. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0021 reserved $0022 tim counter register high (tcnth) see page 231. read: bit 15 14 13 12 11 10 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0023 tim counter register low (tcntl) see page 231. read: bit 7 6 5 4 3 2 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0024 tim modulo register high (tmodh) see page 232. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0025 tim modulo register low (tmodl) see page 232. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0026 tim channel 0 status and control register (tsc0) see page 233. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 4 of 8)
memory map input/output (i/o) section MC68HC708AS48 rev. 4.0 advance information motorola memory map 49 non-disclosure agreement required $0027 tim channel 0 register high (tch0h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 tim channel 0 register low (tch0l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0029 tim channel 1 status and control register (tsc1) see page 233. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $002a tim channel 1 register high (tch1h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b tim channel 1 register low (tch1l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002c tim channel 2 status and control register (tsc2) see page 233. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $002d tim channel 2 register high (tch2h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e tim channel 2 register low (tch2l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002f tim channel 3 status and control register (tsc3) see page 233. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $0030 tim channel 3 register high (tch3h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 5 of 8)
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 50 memory map motorola $0031 tim channel 3 register low (tch3l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0032 tim channel 4 status and control register (tsc4) see page 233. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset: 0 0 0 0 0 0 0 0 $0033 tim channel 4 register high (tch4h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 tim channel 4 register low (tch4l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0035 tim channel 5 status and control register (tsc5) see page 233. read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset: 0 0 0 0 0 0 0 0 $0036 tim channel 5 register high (tch5h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 tim channel 5 register low (tch5l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0038 adc status and control register (adscr) see page 324. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset: 0 0 0 1 1 1 1 1 $0039 adc data register (adr) see page 327. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: r r r r r r r r reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 6 of 8)
memory map input/output (i/o) section MC68HC708AS48 rev. 4.0 advance information motorola memory map 51 non-disclosure agreement required $003a adc input clock register (adiclk) see page 327. read: adiv2 adiv1 adiv0 adiclk 0000 write: r r r r reset: 0 0 0 0 0 0 0 0 $003b bdlc analog and roundtrip delay register (bard) see page 358. read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset: 1 1 0 0 0 1 1 1 $003c bdlc control register 1 (bcr1) see page 360. read: imsg clks r1 r0 00 ie wcm write: r r reset: 1 1 1 0 0 0 0 0 $003d bdlc control register 2 (bcr2) see page 363. read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset: 1 1 0 0 0 0 0 0 $003e bdlc state vector register (bsvr) see page 371. read: 0 0 i3 i2 i1 i0 0 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $003f bdlc data register (bdr) see page 373. read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: indeterminate after reset $fe00 sim break status register (sbsr) see page 144. read: r r r r r r sbsw r write: reset: 0 $fe01 sim reset status register (srsr) see page 146. read: por pin cop ilop ilad 0 lvi 0 write: r r r r r r r r reset: 1 x 0 0 0 0 x 0 $fe03 sim break flag control register (sbfcr) see page 147. read: bcfe r r r r r r r write: reset: 0 $fe07 eprom control register (epmcr) see page 59. read: 0 0 0 0 0 elat 0 epgm write: r r r r r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 7 of 8)
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 52 memory map motorola $fe0c break address register high (brkh) see page 160. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $fe0d break address register low (brkl) see page 160. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $fe0e break status and control register (brkscr) see page 159. read: brke brka 000000 write: r r r r r r reset: 0 0 0 0 0 0 0 0 $fe0f lvi status register (lvisr) see page 152. read: lviout 0 0 0 lvistop lvilck 00 write: r r r r r r reset: 0 0 0 0 0 0 0 0 $fe1c eeprom non-volatile register (eenvr) see page 76. read: eera r r r r eebp2 eebp1 eebp0 write: reset: bits 7, 3, 2, 1, and 0 programmed value or 1 in the erased state. $fe1d eeprom control register (eecr) see page 74. read: eebclk 0 eeoff eeras1 eeras0 eelat 0 eepgm write: r r reset: 0 0 0 0 0 0 0 0 $fe1e reserved $fe1f eeprom array control register (eeacr) see page 76. read: eera r r r r eebp2 eebp1 eebp0 write: r r r r r r r r reset: bits 7, 3, 2, 1, and 0 load their contents from the eenvr register at reset. $ffff cop control register (copctl) see page 175. read: low byte of reset vector write: clear cop counter reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 8 of 8)
memory map input/output (i/o) section MC68HC708AS48 rev. 4.0 advance information motorola memory map 53 non-disclosure agreement required table 2-1. vector addresses address vector low $ffdc bdlc vector (high) $ffdd bdlc vector (low) $ffde adc vector (high) $ffdf adc vector (low) $ffe0 sci transmit vector (high) $ffe1 sci transmit vector (low) $ffe2 sci receive vector (high) $ffe3 sci receive vector (low) $ffe4 sci error vector (high) $ffe5 sci error vector (low) $ffe6 spi transmit vector (high) $ffe7 spi transmit vector (low) $ffe8 spi receive vector (high) $ffe9 spi receive vector (low) $ffea tim over?ow vector (high) $ffeb tim over?ow vector (low) $ffec tim channel 5 vector (high) $ffed tim channel 5 vector (low) $ffee tim channel 4 vector (high) $ffef tim channel 4 vector (low) $fff0 tim channel 3 vector (high) $fff1 tim channel 3 vector (low) $fff2 tim channel 2 vector (high) $fff3 tim channel 2 vector (low) $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) high $fffe reset vector (high) $ffff reset vector (low) priority
non-disclosure agreement required memory map advance information MC68HC708AS48 rev. 4.0 54 memory map motorola
MC68HC708AS48 rev. 4.0 advance information motorola random-access memory (ram) 55 non-disclosure agreement required advance information MC68HC708AS48 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 introduction this section describes the 1,536 bytes of random-access memory (ram). 3.3 functional description addresses $0050C$064f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 1,536-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for input/output (i/o) control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access all page zero ram locations efficiently. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers.
non-disclosure agreement required random-access memory (ram) advance information MC68HC708AS48 rev. 4.0 56 random-access memory (ram) motorola note: for m68hc05, m6805, and m146805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or during the interrupt stacking operation.
MC68HC708AS48 rev. 4.0 advance information motorola erasable programmable read-only memory (eprom/otprom) 57 non-disclosure agreement required advance information MC68HC708AS48 section 4. erasable programmable read-only memory (eprom/otprom) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.4 eprom/otprom control register. . . . . . . . . . . . . . . . . . . . .59 4.5 eprom/otprom programming . . . . . . . . . . . . . . . . . . . . . . .60 4.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.2 introduction this section describes the 49,152 bytes of user non-volatile memory (eprom/otprom) and 36 bytes of user vectors.
non-disclosure agreement required erasable programmable read-only memory advance information MC68HC708AS48 rev. 4.0 58 erasable programmable read-only memory (eprom/otprom) motorola 4.3 functional description the user eprom/otprom consists of 49,152 bytes of user eprom/otprom from addresses $3e00-$fdff and 36 bytes of user interrupt and reset vector eprom/otprom from addresses $fffcC$ffff. see figure 2-1. memory map . note: security has been incorporated into the MC68HC708AS48 to prevent external viewing of the eprom/otprom contents. this feature ensures that customer-developed software remains proprietary. 1 the MC68HC708AS48 with a quartz window (engineering samples only) has 49,152 user bytes and 36 vector bytes of erasable, programmable rom (eprom). the quartz window allows eprom erasure by exposure to ultraviolet light. in the MC68HC708AS48cfn, without the quartz window, the eprom cannot be erased and serves as 49,152 user bytes and 36 vector bytes of one-time programmable rom (otprom). an unprogrammed or erased location reads as $00. the following addresses are user eprom/otprom locations: ? $3e00C$fdff ? $ffdcC$ffff (these locations are reserved for user-defined interrupt and reset vectors.) programming tools are available from motorola. contact your local motorola representative for more information. 1. no security feature is absolutely secure. however, motorolas strategy is to make reading or copying the eprom/otprom difficult for unauthorized users.
erasable programmable read-only memory (eprom/otprom) eprom/otprom control register MC68HC708AS48 rev. 4.0 advance information motorola erasable programmable read-only memory (eprom/otprom) 59 non-disclosure agreement required 4.4 eprom/otprom control register the eprom control register controls eprom/otprom programming. elat eprom/otprom latch control bit this read/write bit latches the address and data buses for programming the eprom/otprom. clearing elat also clears the epgm bit. eprom/otprom data cannot be read when elat is set. 1 = buses configured for eprom/otprom programming 0 = buses configured for normal operation epgm eprom/otprom program control bit this read/write bit applies the programming voltage from the irq/v pp pin to the eprom/otprom. to write to the epgm bit, the elat bit must be set already. reset clears the epgm bit. 1 = eprom/otprom programming power switched on 0 = eprom/otprom programming power switched off address: $fe07 bit 7 654321 bit 0 read: 00000 elat 0 epgm write: rrrrr r reset: 00000000 r = reserved figure 4-1. eprom/otprom control register (epmcr)
non-disclosure agreement required erasable programmable read-only memory advance information MC68HC708AS48 rev. 4.0 60 erasable programmable read-only memory (eprom/otprom) motorola 4.5 eprom/otprom programming the unprogrammed state is a 0. programming changes the state to a 1. use the following procedure to program a byte of eprom/otprom: 1. apply v pp to the irq/v pp pin. see section 14. external interrupt for application information on how to use this pin. 2. set the elat bit. note: writing logic 1s to both the elat and epgm bits with a single instruction sets only the elat bit. epgm must be set by a separate instruction in the programming sequence. 3. write to any user eprom/otprom address. note: writing to an invalid address prevents the programming voltage from being applied. 4. set the epgm bit. 5. wait for a time, t epgm . 6. clear the elat and epgm bits. setting the elat bit configures the address and data buses to latch data for programming the array. only data written to a valid eprom address will be latched. attempts to read any other valid eprom address after step 2 will read the latched data written in step 3. further writes to valid eprom addresses after the first write (step 3) are ignored. the epgm bit cannot be set if the elat bit is cleared. this is to ensure a proper programming sequence. if epgm is set and a valid eprom write occurs, v pp will be applied to the user eprom array. when the epgm bit is cleared, the program voltage is removed from the array.
erasable programmable read-only memory (eprom/otprom) low-power modes MC68HC708AS48 rev. 4.0 advance information motorola erasable programmable read-only memory (eprom/otprom) 61 non-disclosure agreement required 4.6 low-power modes the wait and stop instructions can put the mcu in low-power standby modes. 4.6.1 wait mode the wait instruction does not affect the eprom. 4.6.2 stop mode the stop instruction reduces the eprom power consumption to a minimum. if stop occurs while eprom programming is in progress, high voltage will be removed from the array and the epgm bit will be cleared. to resume programming, clear the elat bit and follow the steps shown in 4.5 eprom/otprom programming .
non-disclosure agreement required erasable programmable read-only memory advance information MC68HC708AS48 rev. 4.0 62 erasable programmable read-only memory (eprom/otprom) motorola
MC68HC708AS48 rev. 4.0 advance information motorola configuration register (config) 63 non-disclosure agreement required advance information MC68HC708AS48 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.2 introduction this section describes the configuration register (config) in the MC68HC708AS48. 5.3 functional description the configuration register options are connections which allow the user to customize the mcu. the options control the enable or disable of the following functions: ? resets caused by the lvi module ? power to the lvi module ? stop mode recovery time (32 cgmxclk cycles or 4096 cgmxclk cycles) ? cop timeout period (8,176 cgmxclk cycles or 262,128 cgmxclk cycles) ? stop instruction ? computer operating properly module (cop) the configuration register ($001f) is used in the initialization of various options. the configuration register can only be written once after each
non-disclosure agreement required con?guration register (config) advance information MC68HC708AS48 rev. 4.0 64 configuration register (config) motorola reset. all of the configuration bits are cleared with reset. since the various options affect the operation of the mcu it is recommended that this register be written immediately after reset. for compatibility, a write to the rom version of this mcu at this location will have no effect. the configuration register may be read at any time. note: the configuration register will allow only one write between resets. 5.4 configuration register lvipwrd lvi power disable bit lvipwrd disables the lvi module. (see section 10. low-voltage inhibit (lvi) .) 1 = lvi module power disabled 0 = lvi module power enabled lvirstd lvi reset disable bit lvirstd disables the reset signal from the lvi module. (see section 10. low-voltage inhibit (lvi) .) 1 = lvi module resets disabled 0 = lvi module resets enabled ssrec short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. (see 16.6.2 stop mode .) 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles address: $001f bit 7 654321 bit 0 read: rr lvirstd lvipwrd ssrec copl stop copd write: rrrrrr reset: unaffected by reset r = reserved figure 5-1. configuration register (config)
configuration register (config) configuration register MC68HC708AS48 rev. 4.0 advance information motorola configuration register (config) 65 non-disclosure agreement required note: if using an external crystal oscillator, do not set the ssrec bit. copl cop long timeout bit copl selects the long cop timeout period. (see section 13. computer operating properly (cop) .) 1 = cop timeout period is 262,128 cgmxclk cycles 0 = cop timeout period is 8,176 cgmxclk cycles stop stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd cop disable bit copd disables the cop module. (see section 13. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled
non-disclosure agreement required con?guration register (config) advance information MC68HC708AS48 rev. 4.0 66 configuration register (config) motorola
MC68HC708AS48 rev. 4.0 advance information motorola electrically erasable programmable rom (eeprom) 67 non-disclosure agreement required advance information MC68HC708AS48 section 6. electrically erasable programmable rom (eeprom) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.4.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.4.2 eeprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.4.3 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . .72 6.4.4 eeprom redundant mode . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.6 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . .74 6.4.7 eeprom non-volatile register and eeprom array configuration register . . . . . . . . . . . . . . . . . . . . .76 6.4.8 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
non-disclosure agreement required electrically erasable programmable rom advance information MC68HC708AS48 rev. 4.0 68 electrically erasable programmable rom (eeprom) motorola 6.2 introduction this section describes the 640 bytes of electrically erasable programmable rom (eeprom). 6.3 features ? byte, block, or bulk erasable ? non-volatile redundant array option ? non-volatile block protection option ? non-volatile mcu configuration bits ? on-chip charge pump for programming/erasing 6.4 functional description addresses $0800C$0a7f are eeprom locations. 640 bytes of eeprom can be programmed or erased without an external voltage supply. the eeprom has a lifetime of 10,000 write-erase cycles in the non-redundant mode. reliability (data retention) is further extended if the redundancy option is selected. eeprom cells are protected with a non-volatile, 128-byte, block protection option. these options are stored in the eeprom non-volatile register (eenvr) and are loaded into the eeprom array configuration register (eeacr) after reset or a read of eenvr. the eeprom array can also be disabled to reduce current. 6.4.1 eeprom programming the unprogrammed state is a logic 1. programming changes the state to a logic 0. only valid eeprom bytes in the non-protected blocks and eenvr can be programmed. when the array is configured in the redundant mode, programming the first 128 bytes ($0800C$087f) will also program the last 128 bytes ($0a00C$0a7f) with the same data. programming the eeprom in the non-redundant mode is recommended. program the data to both locations before entering the redundant mode.
electrically erasable programmable rom (eeprom) functional description MC68HC708AS48 rev. 4.0 advance information motorola electrically erasable programmable rom (eeprom) 69 non-disclosure agreement required follow this procedure to program a byte of eeprom. refer to 21.6 control timing for timing values. 1. clear eeras1 and eeras0 and set eelat in the eecr ($fe1d). set value of t eepgm . (see notes a and b.) 2. write the desired data to any user eeprom address. 3. set the eepgm bit. (see note c.) 4. wait for a time, t eepgm , to program the byte. 5. clear the eepgm bit. 6. wait for the programming voltage time to fall, t eefpv . 7. clear eelat bits. (see note d.) 8. repeat steps 1 through 7 for more eeprom programming. notes: a. eeras1 and eeras0 must be cleared for programming. otherwise, you will be in erase mode. b. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom address will be latched. if another consecutive valid eeprom write occurs, this address and data will override the previous address and data. any attempts to read other eeprom data will read the latched data. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. c. the eepgm bit cannot be set if the eelat bit is cleared and a non-eeprom write has occurred. this is to ensure proper programming sequence. when eepgm is set, the on-board charge pump generates the program voltage and applies it to the user eeprom array. when the eepgm bit is cleared, the program voltage is removed from the array and the internal charge pump is turned off. d. any attempt to clear both eepgm and eelat bits with a single instruction will clear only eepgm to allow time for removal of high voltage from the eeprom array.
non-disclosure agreement required electrically erasable programmable rom advance information MC68HC708AS48 rev. 4.0 70 electrically erasable programmable rom (eeprom) motorola 6.4.2 eeprom erasing the unprogrammed state is a logic 1. only the valid eeprom bytes in the non-protected blocks and eenvr can be erased. when the array is configured in the redundant mode, erasing the first 128 bytes ($0800C$087f) will also erase the last 128 bytes ($0a00C$0a7f). follow this procedure to erase eeprom. refer to 21.6 control timing for timing values. 1. clear/set eeras1 and eeras0 to select byte/block/bulk erase, and set eelat in eectl. set value of t eebyt /t eeblock /t eebulk . (see note a.) 2. write any data to the desired address for byte erase, to any address in the desired block for block erase, or to any array address for bulk erase. 3. set the eepgm bit. (see note b.) 4. wait for a time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for the erasing voltage time to fall, t eefpv ). 7. clear eelat bits. (see note c.) 8. repeat steps 1 through 7 for more eeprom byte/block erasing. eebpx bit must be cleared to erase eeprom data in the corresponding block. if any eebpx is set, the corresponding block cannot be erased and bulk erase mode does not apply. notes: a. setting the eelat bit configures the address and data buses to latch data for erasing the array. only valid eeprom addresses with their data will be latched. if another consecutive valid eeprom write occurs, this address and data will override the previous address and data. in block erase mode, any eeprom address in the block can be used in step 2. all locations within this block will be erased. in bulk erase mode, any eeprom address can be used to erase the whole eeprom. eenvr is not affected with block or bulk
electrically erasable programmable rom (eeprom) functional description MC68HC708AS48 rev. 4.0 advance information motorola electrically erasable programmable rom (eeprom) 71 non-disclosure agreement required erase. any attempts to read other eeprom data will read the latched data. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. b. to ensure proper erasing sequence, the eepgm bit cannot be set if the eelat bit is cleared and a non-eeprom write has occurred. once eepgm is set, the type of erase mode cannot be modified. if eepgm is set, the on-board charge pump generates the erase voltage and applies it to the user eeprom array. when the eepgm bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. c. any attempt to clear both eepgm and eelat bits with a single instruction will clear only eepgm to allow time for removal of high voltage from the eeprom array. in general, all bits should be erased before being programmed. however, if program/erase cycling is of concern, the following procedure can be used to minimize bit cycling in each eeprom byte. if any bit in a byte must be changed from a 0 to a 1, the byte needs to be erased before programming. table 6-1 summarizes the conditions for erasing before programming. table 6-1. eeprom program/erase cycling reduction eeprom data to be programmed eeprom data before programming erase before programming? 00no 01no 10yes 11no
non-disclosure agreement required electrically erasable programmable rom advance information MC68HC708AS48 rev. 4.0 72 electrically erasable programmable rom (eeprom) motorola 6.4.3 eeprom block protection the 640 bytes of eeprom are divided into two 256-byte blocks and one 128-byte block. each of these blocks can be protected separately by the eebpx bit. any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. table 6-2 shows the address ranges within the blocks. if the eebpx bit is set, that corresponding address block is protected. these bits are effective after a reset or a read to the eenvr register. the block protect configuration can be modified by erasing/ programming the corresponding bits in the eenvr register and then reading the eenvr register. in redundant mode eebp2 will have no meaning. table 6-2. eeprom array address blocks block number (eebpx) address range eebp0 $0800C$08ff eebp1 $0900C$09ff eebp2 $0a00C$0a7f
electrically erasable programmable rom (eeprom) functional description MC68HC708AS48 rev. 4.0 advance information motorola electrically erasable programmable rom (eeprom) 73 non-disclosure agreement required 6.4.4 eeprom redundant mode to extend the eeprom data retention, the array can be placed in redundant mode. in this mode, the first 128 bytes of user eeprom array are mapped to the last 128 bytes. reading, programming and erasing of the first 128 eeprom bytes ($0800C$087f) will physically affect two bytes of eeprom. addressing the last 128 bytes will not be recognized. block protection still applies but eebp2 is meaningless. note: before entering redundant mode, program the eeprom in non-redundant mode. 6.4.5 eeprom configuration the eeprom non-volatile register (eenvr) contains configurations concerning block protection and redundancy. eenvr is physically located on the bottom of the eeprom array. the contents are non-volatile and are not modified by reset. on reset, this special register loads the eeprom configuration into a corresponding volatile eeprom array configuration register (eeacr). thereafter, all reads to the eenvr will reload eeacr. the eeprom configuration can be changed by programming/erasing the eenvr like a normal eeprom byte. the new array configuration will take effect with a system reset or a read of the eenvr.
non-disclosure agreement required electrically erasable programmable rom advance information MC68HC708AS48 rev. 4.0 74 electrically erasable programmable rom (eeprom) motorola 6.4.6 eeprom control register this read/write register controls programming/erasing of the array. eebclk eeprom bus clock enable bit this read/write bit determines which clock will be used to drive the internal charge pump for programming/erasing. reset clears this bit. 1 = bus clock drives charge pump. 0 = internal rc oscillator drives charge pump. note: use the internal rc oscillator for applications in the 3 to 5 v range. eeoff eeprom power down bit this read/write bit disables the eeprom module for lower power consumption. any attempts to access the array will give unpredictable results. reset clears this bit. 1 = disable eeprom array 0 = enable eeprom array note: the eeprom requires a recovery time, t eeoff , to stabilize after clearing the eeoff bit. refer to 21.6 control timing for timing values. address: $fe1d bit 7 654321 bit 0 read: eebclk 0 eeoff eeras1 eeras0 eelat 0 eepgm write: r r reset: 00000000 r = reserved figure 6-1. eeprom control register (eecr)
electrically erasable programmable rom (eeprom) functional description MC68HC708AS48 rev. 4.0 advance information motorola electrically erasable programmable rom (eeprom) 75 non-disclosure agreement required eeras1:eeras0 eeprom erase bits these read/write bits set the programming/erasing modes. reset clears these bits. eelat eeprom latch control bit this read/write bit latches the address and data buses for programming the eeprom array. eelat can not be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom programming 0 = buses configured for normal read operation eepgm eeprom program/erase enable bit this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom array if the eelat bit is set and a write to a valid eeprom location has occurred. reset clears the eepgm bit. 1 = eeprom programming/erasing power switched on 0 = eeprom programming/erasing power switched off note: writing logic 0s to both the eelat and eepgm bits with a single instruction will clear only eepgm. this is to allow time for the removal of high voltage. table 6-3. eeprom program/erase mode select eebpx eeras1 eera0 mode 0 0 0 byte program 0 0 1 byte erase 0 1 0 block erase 0 1 1 bulk erase 1 x x no erase/program x = dont care
non-disclosure agreement required electrically erasable programmable rom advance information MC68HC708AS48 rev. 4.0 76 electrically erasable programmable rom (eeprom) motorola 6.4.7 eeprom non-volatile register and eeprom array configuration register these registers configure the eeprom array blocks for programming purposes. eeacr loads its contents from the eenvr register at reset and upon any read of the eenvr register. eera eeprom redundant array bit this programmable/erasable/readable bit in eenvr and read-only bit in eeacr configures the array in redundant mode. reset loads eera from eenvr to eeacr. 1 = eeprom array in redundant mode configuration 0 = eeprom array in normal mode configuration eebp2:eebp0 eeprom block protection bits these programmable/erasable/readable bits in eenvr and read-only bits in eeacr select blocks of eeprom array from being programmed or erased. reset loads eebp[2:0] from eenvr to eeacr. see 6.4.3 eeprom block protection . 1 = eeprom array block protected 0 = eeprom array block unprotected address: $fe1f bit 7 654321 bit 0 read: eera rrrr eebp2 eebp1 eebp0 write: rrrrrrrr eenvr r r r eenvr eenvr eenvr eenvr r = reserved figure 6-2. eeprom array control register (eeacr) address: $fe1c bit 7 654321 bit 0 read: eera rrrr eebp2 eebp1 eebp0 write: reset: pv r r r pv pv pv pv r = reserved pv = programmed value or 1 in the erased state. figure 6-3. eeprom non-volatile register (eenvr)
electrically erasable programmable rom (eeprom) functional description MC68HC708AS48 rev. 4.0 advance information motorola electrically erasable programmable rom (eeprom) 77 non-disclosure agreement required 6.4.8 low-power modes the following subsections describe the low-power modes. 6.4.8.1 wait mode the wait instruction does not affect the eeprom. it is possible to program the eeprom while the mcu is in wait mode. however, if the eeprom is inactive, power can be reduced by setting the eeoff bit before executing the wait instruction. 6.4.8.2 stop mode the stop instruction reduces the eeprom power consumption to a minimum. the stop instruction should not be executed while the high voltage is turned on (eepgm = 1). if stop mode is entered while program/erase is in progress, high voltage will be turned off automatically. however, the eepgm bit will remain set. when stop mode is terminated and if eepgm is still set, the high voltage will be turned back on automatically. program/erase time will need to be extended if program/erase is interrupted by entering stop mode. the module requires a recovery time, t eestop , to stabilize after leaving stop mode (see 21.6 control timing ). attempts to access the array during the recovery time will result in unpredictable behavior.
non-disclosure agreement required electrically erasable programmable rom advance information MC68HC708AS48 rev. 4.0 78 electrically erasable programmable rom (eeprom) motorola
MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 79 non-disclosure agreement required advance information MC68HC708AS48 section 7. central processor unit (cpu) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 7.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 7.4.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .87 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .87 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7.2 introduction this section describes the central processor unit (cpu). the m68hc08 cpu is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture.
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 80 central processor unit (cpu) motorola 7.3 features features of the cpu include: ? fully upward, object-code compatibility with the m68hc05 family ? 16-bit stack pointer with stack manipulation instructions ? 16-bit index register with x-register manipulation instructions ? 8-mhz cpu internal bus frequency ? 64-kbyte program/data memory space ? 16 addressing modes ? memory-to-memory data moves without using accumulator ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? enhanced binary coded decimal (bcd) data handling ? modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes ? low-power stop mode and wait mode
central processor unit (cpu) cpu registers MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 81 non-disclosure agreement required 7.4 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.4.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag twos complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a)
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 82 central processor unit (cpu) motorola 7.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset: 0 0 0 0 0 0 0 0 x x x x x x x x x = indeterminate figure 7-3. index register (h:x)
central processor unit (cpu) cpu registers MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 83 non-disclosure agreement required 7.4.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page zero ($0000 to $00ff) frees direct address (page zero) space. for correct operation, the stack pointer must point only to ram locations. bit 151413121110987654321 bit 0 read: write: reset: 0000000011111111 figure 7-4. stack pointer (sp)
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 84 central processor unit (cpu) motorola 7.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc)
central processor unit (cpu) cpu registers MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 85 non-disclosure agreement required 7.4.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v overflow flag bit the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h half-carry flag bit the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add or adc operation. the half-carry flag is required for binary coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i interrupt mask bit when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled bit 7 6 5 4 3 2 1 bit 0 read: v11h i nzc write: reset: x 1 1 x 1 x x x x = indeterminate figure 7-6. condition code register (ccr)
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 86 central processor unit (cpu) motorola note: to maintain m68hc05 compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n negative flag bit the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z zero flag bit the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c carry/borrow flag bit the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions such as bit test and branch, shift, and rotate also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7
central processor unit (cpu) arithmetic/logic unit (alu) MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 87 non-disclosure agreement required 7.5 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about cpu architecture. 7.6 cpu during break interrupts if the break module is enabled, a break interrupt causes the cpu to execute the software interrupt instruction (swi) at the completion of the current cpu instruction. see section 11. break module (break) . the program counter vectors to $fffcC$fffd ($fefcC$fefd in monitor mode). a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 88 central processor unit (cpu) motorola 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ? (a) + (m) + (c) C imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a ? (a) + (m) C imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp ? (sp) + (16 ? m) C C C C C C imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x ? (h:x) + (16 ? m) C C C C C C imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a ? (a) & (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) CC dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right CC dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? (c) = 0 C C C C C C rel 24 rr 3 c b0 b7 0 b0 b7 c
central processor unit (cpu) instruction set summary MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 89 non-disclosure agreement required bclr n , opr clear bit n in m mn ? 0 CCCCCC dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? (c) = 1 C C C C C C rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? (z) = 1 C C C C C C rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 0 C C C C C C rel 90 rr 3 bgt opr branch if greater than (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 0 C C C C C C rel 92 rr 3 bhcc rel branch if half carry bit clear pc ? (pc) + 2 + rel ? (h) = 0 C C C C C C rel 28 rr 3 bhcs rel branch if half carry bit set pc ? (pc) + 2 + rel ? (h) = 1 C C C C C C rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? (c) | (z) = 0 C C C C C C rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc ? (pc) + 2 + rel ? (c) = 0 C C C C C C rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 C C C C C C rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 C C C C C C rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 1 C C C C C C rel 93 rr 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? (c) = 1 C C C C C C rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? (c) | (z) = 1 C C C C C C rel 23 rr 3 blt opr branch if less than (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 1 C C C C C C rel 91 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? (i) = 0 C C C C C C rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? (n) = 1 C C C C C C rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? (i) = 1 C C C C C C rel 2d rr 3 table 7-1. instruction set summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 90 central processor unit (cpu) motorola bne rel branch if not equal pc ? (pc) + 2 + rel ? (z) = 0 C C C C C C rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? (n) = 0 C C C C C C rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel C C C C C C rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc ? (pc) + 3 + rel ? (mn) = 0 C C C C C dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 C C C C C C rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc ? (pc) + 3 + rel ? (mn) = 1 C C C C C dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn ? 1 CCCCCC dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel C C C C C C rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc ? (pc) + 3 + rel ? (a) C (m) = $00 pc ? (pc) + 3 + rel ? (a) C (m) = $00 pc ? (pc) + 3 + rel ? (x) C (m) = $00 pc ? (pc) + 3 + rel ? (a) C (m) = $00 pc ? (pc) + 2 + rel ? (a) C (m) = $00 pc ? (pc) + 4 + rel ? (a) C (m) = $00 CCCCCC dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c ? 0 C C C C C 0 inh 98 1 cli clear interrupt mask i ? 0 C C 0 C C C inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m ? $00 a ? $00 x ? $00 h ? $00 m ? $00 m ? $00 m ? $00 0CC01C dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 7-1. instruction set summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) instruction set summary MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 91 non-disclosure agreement required cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) C (m) CC imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (m) x ? ( x) = $ff C (m) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 0CC 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) C (m:m + 1) CC imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) C (m) CC imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 uCC inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a ? (a) C 1 or m ? (m) C 1 or x ? (x)C1 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 4 + rel ? (result) 1 0 CCCCCC dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 m ? (m) C 1 CC C dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a ? (h:a)/(x) h ? remainder CCCC inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a ? (a ? m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 92 central processor unit (cpu) motorola inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 m ? (m) + 1 CC C dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ? jump address C C C C C C dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n ( n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? unconditional address CCCCCC dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a ? (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ? ( m:m + 1 ) 0CC C imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ? (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) CC dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right CC0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ? (m) source h:x ? (h:x) + 1 (ix+d, dix+) 0CC C dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ? (x) (a) C 0 C C C 0 inh 42 5 table 7-1. instruction set summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) instruction set summary MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 93 non-disclosure agreement required neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) CC dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none C C C C C C inh 9d 1 nsa nibble swap a a ? (a[3:0]:a[7:4]) C C C C C C inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a ? (a) | (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ? (sp ) C 1 C C C C C C inh 87 2 pshh push h onto stack push (h) ; sp ? (sp ) C 1 CCCCCCinh 8b 2 pshx push x onto stack push (x) ; sp ? (sp ) C 1 CCCCCCinh 89 2 pula pull a from stack sp ? (sp + 1); pull ( a ) CCCCCCinh 86 2 pulh pull h from stack sp ? (sp + 1); pull ( h ) CCCCCCinh 8a 2 pulx pull x from stack sp ? (sp + 1); pull ( x ) CCCCCCinh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry CC dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry CC dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp ? $ff C C C C C C inh 9c 1 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp ? sp + 1 ; pull ( pch) sp ? sp + 1; pull (pcl) CCCCCCinh 81 4 table 7-1. instruction set summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
non-disclosure agreement required central processor unit (cpu) advance information MC68HC708AS48 rev. 4.0 94 central processor unit (cpu) motorola sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ? (a) C (m) C (c) CC imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c ? 1 C C C C C 1 inh 99 1 sei set interrupt mask i ? 1 C C 1 C C C inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m ? (a) 0 C C C dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ? (h:x) 0 C C C dir 35 dd 4 stop enable irq pin; stop oscillator i ? 0; stop oscillator C C 0 C C C inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m ? (x) 0 C C C dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ? (a) C (m) CC imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte CC1CCCinh 83 9 tap transfer a to ccr ccr ? (a) inh 84 2 tax transfer a to x x ? (a) C C C C C C inh 97 1 tpa transfer ccr to a a ? (ccr) C C C C C C inh 85 1 table 7-1. instruction set summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) opcode map MC68HC708AS48 rev. 4.0 advance information motorola central processor unit (cpu) 95 non-disclosure agreement required 7.8 opcode map the opcode map is provided in table 7-2 . tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) C $00 or (x) C $00 or (m) C $00 0 C C C dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x ? (sp) + 1 C C C C C C inh 95 2 txa transfer x to a a ? (x) C C C C C C inh 9f 1 txs transfer h:x to sp (sp) ? (h:x) C 1 C C C C C C inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u unde?ned h index register high byte v over?ow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode ? loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit not affected table 7-1. instruction set summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
non-disclosure agreement required advance information MC68HC708AS48 rev. 4.0 96 central processor unit (cpu) motorola central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3 dir 4 bset0 2 dir 3 bra 2 rel 4 neg 2 dir 1 nega 1 inh 1 negx 1 inh 4 neg 2 ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1 inh 3 bge 2 rel 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 4 sub 3 ix2 5 sub 4 sp2 3 sub 2 ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3 dir 4 bclr0 2 dir 3 brn 2 rel 5 cbeq 3 dir 4 cbeqa 3 imm 4 cbeqx 3 imm 5 cbeq 3 ix1+ 6 cbeq 4 sp1 4 cbeq 2 ix+ 4 rts 1 inh 3 blt 2 rel 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 4 cmp 3 ix2 5 cmp 4 sp2 3 cmp 2 ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3 dir 4 bset1 2 dir 3 bhi 2 rel 5 mul 1 inh 7 div 1 inh 3 nsa 1 inh 2 daa 1 inh 3 bgt 2 rel 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 4 sbc 3 ix2 5 sbc 4 sp2 3 sbc 2 ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3 dir 4 bclr1 2 dir 3 bls 2 rel 4 com 2 dir 1 coma 1 inh 1 comx 1 inh 4 com 2 ix1 5 com 3 sp1 3 com 1ix 9 swi 1 inh 3 ble 2 rel 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 4 cpx 3 ix2 5 cpx 4 sp2 3 cpx 2 ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3 dir 4 bset2 2 dir 3 bcc 2 rel 4 lsr 2 dir 1 lsra 1 inh 1 lsrx 1 inh 4 lsr 2 ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1 inh 2 txs 1 inh 2 and 2 imm 3 and 2 dir 4 and 3 ext 4 and 3 ix2 5 and 4 sp2 3 and 2 ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3 dir 4 bclr2 2 dir 3 bcs 2 rel 4 sthx 2 dir 3 ldhx 3 imm 4 ldhx 2 dir 3 cphx 3 imm 4 cphx 2 dir 1 tpa 1 inh 2 tsx 1 inh 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 4 bit 3 ix2 5 bit 4 sp2 3 bit 2 ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3 dir 4 bset3 2 dir 3 bne 2 rel 4 ror 2 dir 1 rora 1 inh 1 rorx 1 inh 4 ror 2 ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1 inh 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 4 lda 3 ix2 5 lda 4 sp2 3 lda 2 ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3 dir 4 bclr3 2 dir 3 beq 2 rel 4 asr 2 dir 1 asra 1 inh 1 asrx 1 inh 4 asr 2 ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1 inh 1 ta x 1 inh 2 ais 2 imm 3 sta 2 dir 4 sta 3 ext 4 sta 3 ix2 5 sta 4 sp2 3 sta 2 ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3 dir 4 bset4 2 dir 3 bhcc 2 rel 4 lsl 2 dir 1 lsla 1 inh 1 lslx 1 inh 4 lsl 2 ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1 inh 1 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 4 eor 3 ix2 5 eor 4 sp2 3 eor 2 ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3 dir 4 bclr4 2 dir 3 bhcs 2 rel 4 rol 2 dir 1 rola 1 inh 1 rolx 1 inh 4 rol 2 ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1 inh 1 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 4 adc 3 ix2 5 adc 4 sp2 3 adc 2 ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3 dir 4 bset5 2 dir 3 bpl 2 rel 4 dec 2 dir 1 deca 1 inh 1 decx 1 inh 4 dec 2 ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1 inh 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 4 ora 3 ix2 5 ora 4 sp2 3 ora 2 ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3 dir 4 bclr5 2 dir 3 bmi 2 rel 5 dbnz 3 dir 3 dbnza 2 inh 3 dbnzx 2 inh 5 dbnz 3 ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1 inh 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 4 add 3 ix2 5 add 4 sp2 3 add 2 ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3 dir 4 bset6 2 dir 3 bmc 2 rel 4 inc 2 dir 1 inca 1 inh 1 incx 1 inh 4 inc 2 ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1 inh 1 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix d 5 brclr6 3 dir 4 bclr6 2 dir 3 bms 2 rel 3 tst 2 dir 1 tsta 1 inh 1 tstx 1 inh 3 tst 2 ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1 inh 4 bsr 2 rel 4 jsr 2 dir 5 jsr 3 ext 6 jsr 3 ix2 5 jsr 2 ix1 4 jsr 1ix e 5 brset7 3 dir 4 bset7 2 dir 3 bil 2 rel 5 mov 3dd 4 mov 2 dix+ 4 mov 3 imd 4 mov 2 ix+d 1 stop 1 inh * 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 4 ldx 3 ix2 5 ldx 4 sp2 3 ldx 2 ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3 dir 4 bclr7 2 dir 3 bih 2 rel 3 clr 2 dir 1 clra 1 inh 1 clrx 1 inh 3 clr 2 ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1 inh 1 txa 1 inh 2 aix 2 imm 3 stx 2 dir 4 stx 3 ext 4 stx 3 ix2 5 stx 4 sp2 3 stx 2 ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3 dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 97 non-disclosure agreement required advance information MC68HC708AS48 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.4.1 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.4.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . .101 8.4.2.1 circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . .103 8.4.2.3 manual and automatic pll bandwidth modes . . . . . . .103 8.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . .107 8.4.3 base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . .107 8.4.4 cgm external connections. . . . . . . . . . . . . . . . . . . . . . . .108 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 8.5.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . .109 8.5.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . .109 8.5.3 external filter capacitor pin (cgmxfc). . . . . . . . . . . . . .109 8.5.4 analog power pin (v dda /v ddaref ). . . . . . . . . . . . . . . . . .110 8.5.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . .110 8.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . .110 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . .110 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . .110 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . .114 8.6.3 pll programming register . . . . . . . . . . . . . . . . . . . . . . . .116 8.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 98 clock generator module (cgm) motorola 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.9 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . .119 8.10 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . .119 8.10.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . .119 8.10.2 parametric influences on reaction time . . . . . . . . . . . . .121 8.10.3 choosing a filter capacitor. . . . . . . . . . . . . . . . . . . . . . . .122 8.10.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . .123 8.2 introduction this section describes the clock generator module (cgm). the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system integration module (sim) derives the system clocks. cgmout is based on either the crystal clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequency generator designed for use with 1-mhz to 16-mhz crystals or ceramic resonators. the pll can generate an 8-mhz bus frequency without using a 32-mhz crystal. 8.3 features features of the cgm include: ? phase-locked loop with output frequency in integer multiples of the crystal reference ? programmable hardware voltage-controlled oscillator (vco) for low-jitter operation ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? cpu interrupt on entry or exit from locked condition
clock generator module (cgm) functional description MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 99 non-disclosure agreement required 8.4 functional description the cgm consists of three major submodules: ? crystal oscillator circuit the crystal oscillator circuit generates the constant crystal frequency clock, cgmxclk. ? phase-locked loop (pll) the pll generates the programmable vco frequency clock cgmvclk. ? base clock selector circuit this software-controlled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base clock, cgmout. the sim derives the system clocks from cgmout. figure 8-1 shows the structure of the cgm. 8.4.1 crystal oscillator circuit the crystal oscillator circuit consists of an inverting amplifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the output. the simoscen signal from the system integration module (sim) enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to produce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator circuit. connect the external clock to the osc1 pin and let the osc2 pin float.
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 100 clock generator module (cgm) motorola figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog ? 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cgmxfc v ss v dda osc1 osc2 to sim, sci, adc, to sim ptc3 monitor mode a b s* user mode *when s = 1, cgmout = b bdlc, cop
clock generator module (cgm) functional description MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 101 non-disclosure agreement required 8.4.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. refer to 21.9 cgm operating conditions for operating frequencies while reading this section. 8.4.2.1 circuits the pll consists of these circuits: ? voltage-controlled oscillator (vco) ? modulo vco frequency divider ? phase detector ? loop filter ? lock detector addr. register name bit 7 6 5 4 3 2 1 bit 0 $001c pll control register (pctl) see page 112. read: pllie pllf pllon bcs 1111 write: r r r r r reset: 0 0 1 0 1 1 1 1 $001d pll bandwidth control register (pbwc) see page 114. read: auto lock a cq xld 0000 write: r r r r r reset: 0 0 0 0 0 0 0 0 $001e pll programming register (ppg) see page 116. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 r = reserved figure 8-2. cgm i/o register summary
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 102 clock generator module (cgm) motorola the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. (for maximum immunity guidelines, refer to document numbers an1050/d and an1263/d on electromagnetic compatibility available from your motorola sales office.) the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , 4.9152 mhz times a linear factor (l) or f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a crystal frequency, f rclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency equal to f rclk . the vcos output clock, cgmvclk, running at a frequency f vclk is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor, n (see 8.4.2.4 programming the pll ). the dividers output is the vco feedback clock, cgmvdv, running at a frequency equal to f vclk /n. see 21.9 cgm operating conditions for more information. the phase detector then compares the vco feedback clock (cgmvdv) with the final reference clock (cgmrdv). a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connected to cgmxfc, based on the width and direction of the correction pulse. the filter can make fast or slow corrections, depending on its mode, described in 8.4.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency, f rd . the circuit determines the mode of the pll and the lock condition based on this comparison.
clock generator module (cgm) functional description MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 103 non-disclosure agreement required 8.4.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: ? acquisition mode in acquisition mode, the filter can make large (see 21.11 cgm acquisition/lock time information ) frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register (see 8.6.2 pll bandwidth control register .) ? tracking mode in tracking mode, the filter makes only small (see 21.11 cgm acquisition/lock time information ) corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 8.4.3 base clock selector circuit .) the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. 8.4.2.3 manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode also is used to determine when the vco clock, cgmvclk, is safe to use as the source for the base clock, cgmout. (see 8.6.2 pll bandwidth control register .) if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll startup, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. (see 8.4.3 base clock selector circuit .) if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 104 clock generator module (cgm) motorola software must take appropriate action, depending on the application. (see 8.7 interrupts for information and precautions on using interrupts.) the following conditions apply when the pll is in automatic bandwidth control mode: ? the acq bit (see 8.6.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. (see 8.4.2.2 acquisition and tracking modes .) ? the acq bit is set when the vco frequency is within a certain tolerance, d trk , and is cleared when the vco frequency is out of a certain tolerance, d unt . (see 8.10 acquisition/lock time specifications for more information.) ? the lock bit is a read-only indicator of the locked state of the pll. ? the lock bit is set when the vco frequency is within a certain tolerance, d lock , and is cleared when the vco frequency is out of a certain tolerance, d unl . (see 8.10 acquisition/lock time specifications for more information.) ? cpu interrupts can occur if enabled (pllie = 1) when the plls lock condition changes, toggling the lock bit. (see 8.6.1 pll control register .) the pll also can operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. the following conditions apply when in manual mode: ? acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. ? before entering tracking mode ( acq = 1), software must wait a given time, t acq (see 8.10 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control register (pctl).
clock generator module (cgm) functional description MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 105 non-disclosure agreement required ? software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). ? the lock bit is disabled. ? cpu interrupts from the cgm are disabled. 8.4.2.4 programming the pll use this procedure to program the pll: 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desired vco frequency, f vclkdes . f vclkdes = 4 f busdes example: f vclkdes = 4 8 mhz = 32 mhz 3. using a reference frequency, f rclk , equal to the crystal frequency, calculate the vco frequency multiplier, n. note: the round function means that the result is rounded to the nearest integer. example: 4. calculate the vco frequency, f vclk . example: f vclk = 8 4 mhz = 32 mhz n round f vclkdes f rclk --------------------- - ? ?? = n 32 mhz 4 mhz -------------------- =8 = f vclk nf rclk =
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 106 clock generator module (cgm) motorola 5. calculate the bus frequency, f bus , and compare f bus with f busdes . if the calculated f bus is not within the tolerance limits of your application, select another f busdes or another f rclk . example: 6. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. example: 7. calculate the vco center-of-range frequency, f vrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f vrs = l f nom example: f vrs = 7 4.9152 mhz = 34.4 mhz note: exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. for proper operation, 8. program the pll registers accordingly: a. in the upper four bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower four bits of the pll programming register (ppg), program the binary equivalent of l. f bus f vclk 4 ----------- - = f bus 32 mhz 4 -------------------- = 8 mhz = l round f vclk f nom ------------ - ? ?? = l 32 mhz 4.9152 mhz ------------------------------- - = 7 = f vrs f vclk C f nom 2 -------------- -
clock generator module (cgm) functional description MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 107 non-disclosure agreement required 8.4.2.5 special programming exceptions the programming method described in 8.4.2.4 programming the pll does not account for two possible exceptions. a value of 0 for n or l is meaningless when used in the equations given. to account for these exceptions: ? a 0 value for n is interpreted exactly the same as a value of 1. ? a 0 value for l disables the pll and prevents its selection as the source for the base clock. (see 8.4.3 base clock selector circuit .) 8.4.3 base clock selector circuit this circuit is used to select either the crystal clock (cgmxclk) or the vco clock (cgmvclk) as the source of the base clock (cgmout). the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock.
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 108 clock generator module (cgm) motorola 8.4.4 cgm external connections in its typical configuration, the cgm requires seven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 8-3 . figure 8-3 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: ? crystal, x 1 ? fixed capacitor, c 1 ? tuning capacitor, c 2 , can also be a fixed capacitor ? feedback resistor, r b ? series resistor, r s , optional the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. refer to the crystal manufacturers data for more information. figure 8-3 also shows the external components for the pll: ? bypass capacitor, c byp ? filter capacitor, c f routing should be done with great care to minimize signal cross talk and noise. (see 8.10 acquisition/lock time specifications for routing information and more information on the filter capacitors value and its effects on pll performance.)
clock generator module (cgm) i/o signals MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 109 non-disclosure agreement required figure 8-3. cgm external connections 8.5 i/o signals the following paragraphs describe the cgm i/o signals. 8.5.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 8.5.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 8.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. a small external capacitor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the c f connection. c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp osc1 osc2 v ss cgmxfc v dda /v ddaref *r s can be 0 (shorted) when used with higher-frequency crystals. refer to manufacturers data. v dd
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 110 clock generator module (cgm) motorola 8.5.4 analog power pin (v dda /v ddaref ) v dda /v ddaref is a power pin used by the analog portions of the pll. connect the v dda /v ddaref pin to the same voltage potential as the v dd pin. note: route v dda /v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.5 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator and pll. 8.5.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal, f xclk , and comes directly from the crystal oscillator circuit. figure 8-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. 8.5.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. 8.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector.
clock generator module (cgm) cgm registers MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 111 non-disclosure agreement required 8.6 cgm registers these registers control and monitor operation of the cgm: ? pll control register (pctl) (see 8.6.1 pll control register .) ? pll bandwidth control register (pbwc) (see 8.6.2 pll bandwidth control register .) ? pll programming register (ppg) (see 8.6.3 pll programming register .) figure 8-4 is a summary of the cgm registers. addr. register name bit 7 6 5 4 3 2 1 bit 0 $001c pll control register (pctl) see page 112. read: pllie pllf pllon bcs 1111 write: r r r r r reset: 0 0 1 0 1 1 1 1 $001d pll bandwidth control register (pbwc) see page 114. read: auto lock a cq xld 0000 write: r r r r r reset: 0 0 0 0 0 0 0 0 $001e pll programming register (ppg) see page 116. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 r = reserved notes: 1. when auto = 0, pllie is forced to logic 0 and is read-only. 2. when auto = 0, pllf and lock read as logic 0. 3. when auto = 1, a cq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic 0 and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-4. cgm i/o register summary
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 112 clock generator module (cgm) motorola 8.6.1 pll control register the pll control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. pllie pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf pll flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as logic 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently clear the pllf bit. any read or read-modify-write operation on the pll control register clears the pllf bit. address: $001c bit 7 654321 bit 0 read: pllie pllf pllon bcs 1111 write: r rrrr reset: 00101111 r = reserved figure 8-5. pll control register (pctl)
clock generator module (cgm) cgm registers MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 113 non-disclosure agreement required pllon pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see 8.4.3 base clock selector circuit .) reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmvclk cycles to complete the transition from one source clock to the other. during the transition, cgmout is held in stasis. (see 8.4.3 base clock selector circuit .) reset and the stop instruction clear the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. (see 8.4.3 base clock selector circuit .) pctl[3:0] unimplemented bits these bits provide no function and always read as logic 1s.
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 114 clock generator module (cgm) motorola 8.6.2 pll bandwidth control register the pll bandwidth control register: ? selects automatic or manual (software-controlled) bandwidth control mode ? indicates when the pll is locked ? in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode auto automatic bandwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked address: $001d bit 7 654321 bit 0 read: auto lock a cq xld 0000 write: r rrrr reset: 00000000 r = reserved figure 8-6. pll bandwidth control register (pbwc)
clock generator module (cgm) cgm registers MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 115 non-disclosure agreement required acq acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld crystal loss detect bit when the vco output (cgmvclk) is driving cgmout, this read/write bit can indicate whether the crystal reference frequency is active or not. to check the status of the crystal reference, follow these steps: 1. write a logic 1 to xld. 2. wait n 4 cycles. (n is the vco frequency multiplier.) 3. read xld. 1 = crystal reference not active 0 = crystal reference active the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as logic 0. pbwc[3:0] reserved for test these bits enable test functions not available in user mode. to ensure software portability from development systems to user applications, software should write 0s to pbwc[3:0] whenever writing to pbwc.
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 116 clock generator module (cgm) motorola 8.6.3 pll programming register the pll programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul[7:4] multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier, n. (see 8.4.2 phase-locked loop circuit (pll) .) a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. reset initializes these bits to $6 to give a default multiply value of 6. address: $001e bit 7 654321 bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 r = reserved figure 8-7. pll programming register (ppg) table 8-1. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15
clock generator module (cgm) interrupts MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 117 non-disclosure agreement required note: the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs[7:4] vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency, f vrs , (see 8.4.2 phase-locked loop circuit (pll) .) vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see 8.4.2.5 special programming exceptions .) a value of $0 in the vco range selects bits, disables the pll, and clears the bcs bit in the pctl. (see 8.4.3 base clock selector circuit and 8.4.2.5 special programming exceptions for more information.) reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency sensitive,
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 118 clock generator module (cgm) motorola interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 8.8 special modes the wait and stop instructions put the mcu in low-power standby modes. 8.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 8.8.2 stop mode when the stop instruction executes, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco clock (cgmvclk) divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the crystal clock (cgmxclk) divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear.
clock generator module (cgm) cgm during break interrupts MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 119 non-disclosure agreement required 8.9 cgm during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. 8.10 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensures the highest stability and lowest acquisition/lock times. 8.10.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operating at 1 mhz and suffers a C100 khz noise hit, the acquisition time
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 120 clock generator module (cgm) motorola is the time taken to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. the discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are as follows: ? acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, d trk . acquisition time is based on an initial frequency error, [(f des C f orig )/f des ], of not more than 100%. in automatic bandwidth control mode (see 8.4.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). ? lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, d lock . lock time is based on an initial frequency error, [(f des Cf orig )/f des ], of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). (see 8.4.2.3 manual and automatic pll bandwidth modes .) obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases.
clock generator module (cgm) acquisition/lock time specifications MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 121 non-disclosure agreement required 8.10.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the pll reaction times is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of an external crystal frequency, f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 8.10.3 choosing a filter capacitor .) also important is the operating voltage potential applied to the pll analog portion potential (v dda /v ddaref ). typically v dda /v ddaref is at the same potential as v dd . the power supply potential alters the characteristics of the pll. a fixed value is best. variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll.
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 122 clock generator module (cgm) motorola temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 8.10.3 choosing a filter capacitor as described in 8.10.2 parametric influences on reaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency, f rdv , and supply voltage, v dd . the value of the capacitor, therefore, must be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to the following equation. refer to 8.4.2 phase-locked loop circuit (pll) for the value of f rdv and 21.10 cgm component information for the value of c fact . for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonly available capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the pll can become unstable. also, always choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. c f c fact v dda f rdv ------------ - ? ?? =
clock generator module (cgm) acquisition/lock time specifications MC68HC708AS48 rev. 4.0 advance information motorola clock generator module (cgm) 123 non-disclosure agreement required 8.10.4 reaction time calculation the actual acquisition and lock times can be calculated using the equations in this subsection. these equations yield nominal values under the following conditions: ? correct selection of filter capacitor, c f (see 8.10.3 choosing a filter capacitor .) ? room temperature operation ? negligible external leakage on cgmxfc ? negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. (see 8.4.2.2 acquisition and tracking modes .) note: there is an inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (see 8.4.2.3 manual and automatic pll bandwidth modes .) a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, d trk , before exiting acquisition mode. additionally, a certain number of clock cycles, n trk , is required to ascertain that the pll is within the lock mode entry tolerance, d lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . refer to 8.4.2 phase-locked loop circuit (pll) for the value of f rdv . t acq v dda f rdv ----------------- ? ? ?? 8 k acq ----------------- ? ?? = t al v dda f rdv ----------------- ? ? ?? 4 k trk ---------------- ? ?? = t lock t acq t al + =
non-disclosure agreement required clock generator module (cgm) advance information MC68HC708AS48 rev. 4.0 124 clock generator module (cgm) motorola also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see 8.4.3 base clock selector circuit ), because the factors described in 8.10.2 parametric influences on reaction time can slow the lock time considerably.
MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 125 non-disclosure agreement required advance information MC68HC708AS48 section 9. system integration module (sim) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . .129 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.3.2 clock startup from por or lvi reset. . . . . . . . . . . . . . . .129 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . .130 9.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . .130 9.4.1 external pin reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.4.2 active resets from internal sources . . . . . . . . . . . . . . . . .132 9.4.2.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 9.4.2.2 computer operating properly (cop) reset. . . . . . . . . .134 9.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . .134 9.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .134 9.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . .134 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 9.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . .135 9.5.2 sim counter during stop mode recovery . . . . . . . . . . . .135 9.5.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . .135 9.6 program exception control. . . . . . . . . . . . . . . . . . . . . . . . . . .136 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.6.3 break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.6.4 status flag protection in break mode. . . . . . . . . . . . . . . .140 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 126 system integration module (sim) motorola 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.8.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . .144 9.8.2 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.8.3 sim break flag control register. . . . . . . . . . . . . . . . . . . .147 9.2 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. the sim is a system state controller that coordinates cpu and exception timing. together with the central processor unit (cpu), the sim controls all mcu activities. a block diagram of the sim is shown in figure 9-1 . figure 9-2 is a summary of the sim input/output (i/o) registers. the sim is responsible for: ? bus clock generation and control for cpu and peripherals C stop/wait/reset/break entry and recovery C internal clock control ? master reset control, including power-on reset (por) and computer operating properly (cop) timeout ? interrupt control C acknowledge timing C arbitration control timing C vector address generation ? cpu enable/disable timing ? modular architecture expandable to 128 interrupt sources
system integration module (sim) introduction MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 127 non-disclosure agreement required figure 9-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop from cpu cpu wait from cpu simoscen to cgm cgmout from cgm internal clocks master reset control reset pin logic lvi from lvi module illegal opcode from cpu illegal address from address map decoders cop from cop module interrupt sources cpu interface reset control sim counter cop clock cgmxclk from cgm ? 2
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 128 system integration module (sim) motorola table 9-1 shows the internal signal names used in this section. addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe00 sim break status register (sbsr) see page 144. read: r r r r r r sbsw r write: reset: 0 $fe01 sim reset status register (srsr) see page 146. read: por pin cop ilop ilad 0 lvi 0 write: r r r r r r r r reset: 1 x 0 0 0 0 x 0 $fe03 sim break flag control register (sbfcr) see page 147. read: bcfe r r r r r r r write: reset: 0 r = reserved x = indeterminate figure 9-2. sim i/o register summary table 9-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/ w read/write signal
system integration module (sim) sim bus clock control and generation MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 129 non-disclosure agreement required 9.3 sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 9-3 . this clock can come from either an external oscillator or from the on-chip pll. (see section 8. clock generator module (cgm) .) 9.3.1 bus timing in user mode , the internal bus frequency is either the crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. (see section 8. clock generator module (cgm) .) 9.3.2 clock startup from por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after 4096 cgmxclk cycles. the rst pin is driven low by the sim during this entire period. the bus clocks start upon completion of the timeout. figure 9-3. cgm clock signals pll osc1 cgmxclk ? 2 bus clock generators sim cgm sim counter ptc3 monitor mode clock select circuit cgmvclk bcs ? 2 a b s* cgmout *when s = 1, cgmout = b user mode
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 130 system integration module (sim) motorola 9.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 9.7.2 stop mode .) in wait mode, the cpu clocks are inactive. however, some modules can be programmed to be active in wait mode. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. 9.4 reset and system initialization the mcu has these reset sources: ? power-on reset module (por) ? external reset pin ( rst) ? computer operating properly module (cop) ? low-voltage inhibit module (lvi) ? illegal opcode ? illegal address each of these resets produces the vector $fffeCffff ($fefeCfeff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 9.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 9.8 sim registers .)
system integration module (sim) reset and system initialization MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 131 non-disclosure agreement required 9.4.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 9-2 for details. figure 9-4 shows the relative timing. figure 9-4. external reset timing table 9-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 132 system integration module (sim) motorola 9.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. see figure 9-5 . an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. (see figure 9-6 .) note that for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 9-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. figure 9-5. internal reset timing figure 9-6. sources of internal reset irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset
system integration module (sim) reset and system initialization MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 133 non-disclosure agreement required 9.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin ( rst) is held low while the sim counter counts out 4096 cgmxclk cycles. another 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: ? a por pulse is generated. ? the internal reset signal is asserted. ? the sim enables cgmout. ? internal clocks to the cpu and modules are held inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. ? the rst pin is driven low during the oscillator stabilization time. ? the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 9-7. por recovery porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 134 system integration module (sim) motorola 9.4.2.2 computer operating properly (cop) reset the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr) if the copd bit in the config register is at logic 0. (see section 13. computer operating properly (cop) .) 9.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. note: a $9e opcode (pre-byte for sp instructions) followed by an $8e opcode (stop instruction) generates a stop mode recovery reset. if the stop enable bit, stop, in the config register is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. 9.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. 9.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit (lvi) module asserts its output to the sim when the v dd voltage falls to the v lvii voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwrd and lvirstd bits in the config register are at logic 0. the rst pin will be held low until the sim counts 4096 cgmxclk cycles after v dd rises above v lvir . another 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. (see section 10. low-voltage inhibit (lvi) .)
system integration module (sim) sim counter MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 135 non-disclosure agreement required 9.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clocked by the falling edge of cgmxclk. 9.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation module (cgm) to drive the bus clock state machine. 9.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the config register. if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. 9.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 9.7.2 stop mode for details.) the sim counter is free-running after all reset states. (see 9.4.2 active resets from internal sources for counter control and internal reset recovery sequences.)
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 136 system integration module (sim) motorola 9.6 program exception control normal, sequential program execution can be changed in three different ways: ? interrupts C maskable hardware cpu interrupts C non-maskable software interrupt instruction (swi) ? reset ? break interrupts 9.6.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 9-8 shows interrupt entry timing. figure 9-10 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the i bit is cleared. (see figure 9-9 .) figure 9-8. interrupt entry timing module interrupt iab idb last address sp vector addr. high vector addr. low new pc new pc + 1 pc C 1 high byte vector high vector low sp C 1 sp C 2 sp C 3 sp C 4 pc C 1 low byte x a ccr opcode r/ w end of last instr.
system integration module (sim) program exception control MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 137 non-disclosure agreement required figure 9-9. interrupt processing no no no yes no no yes yes i bit set? from reset break interrupt? i bit set? hardware interrupt? swi instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. yes yes execute instruction. rti instruction?
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 138 system integration module (sim) motorola figure 9-10. interrupt recovery timing 9.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 9-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m68hc05, m6805, and m146805 families, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. iab idb sp C 3 ccr sp C 2 sp C 1 sp pc C 1 opcode operand sp C 4 pc pc + 1 ax high byte pc C 1 low byte rti address irrelevant data rti addr. + 1 rti opcode module interrupt r/ w
system integration module (sim) program exception control MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 139 non-disclosure agreement required figure 9-11 . interrupt recognition example 9.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc C 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 140 system integration module (sim) motorola 9.6.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. 9.6.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (see section 11. break module (break) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how the break state affects each module. 9.6.4 status flag protection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select to protect flags from being cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). (see 9.8.3 sim break flag control register .) protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism for example, a read of one register followed by the read or write of another are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as usual.
system integration module (sim) low-power modes MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 141 non-disclosure agreement required 9.7 low-power modes executing the wait or stop instruction puts the mcu in a low-power mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 9.7.1 wait mode in wait mode, the cpu clocks are inactive while one set of peripheral clocks continues to run. figure 9-12 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration (config, $001f) register is logic 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 9-12. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/ w note: previous data can be operand data or the wait opcode, depending on the last instruction.
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 142 system integration module (sim) motorola figure 9-13 and figure 9-14 show the timing for wait recovery. figure 9-13. wait recovery from interrupt or break figure 9-14. wait recovery from internal reset 9.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the short stop recovery (ssrec) bit in the config register ($001f). if ssrec is set, stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles
system integration module (sim) low-power modes MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 143 non-disclosure agreement required ideal for applications using canned oscillators that do not require long startup times from stop mode. note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 9-15 shows stop mode entry timing. figure 9-15. stop mode entry timing figure 9-16. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/ w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp C 1 sp C 2 sp C 3 stop +1 stop recovery period
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 144 system integration module (sim) motorola 9.8 sim registers the sim has three memory mapped registers. 9.8.1 sim break status register the sim break status register contains a flag to indicate that a break caused an exit from stop mode or wait mode. sbsw sim break stop/wait bit this status bit is useful in applications requiring a return to wait mode or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode exited by break interrupt 0 = stop mode or wait mode not exited by break interrupt address: $fe00 bit 7 654321 bit 0 read: rrrrrr sbsw r write: reset: 0 r = reserved figure 9-17. sim break status register (sbsr)
system integration module (sim) sim registers MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 145 non-disclosure agreement required sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. writing 0 to the sbsw bit clears it. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register.
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 146 system integration module (sim) motorola 9.8.2 reset status register this read-only register contains flags to show reset sources. a power-on reset sets the por flag and clears all other flags. reset sources other than power-on reset do not clear all other flags. reading the reset status register clears all reset flags. reset service can read the reset status register to clear the register after power-on reset and to determine the source of any subsequent reset. note: only a read of the reset status register clears all reset flags. after multiple resets from different sources without reading the register, multiple flags remain set. por power-on reset flag 1 = power-on reset since last read of rsr 0 = read of rsr since last power-on reset pin external reset flag 1 = external reset since last read of rsr 0 = power-on reset or read of rsr since last external reset cop cop reset flag 1 = cop reset since last read of rsr 0 = power-on reset or read of rsr since last cop reset ilop illegal opcode reset flag 1 = illegal opcode reset since last read of rsr 0 = power-on reset or read of rsr since last illegal opcode reset address: $fe01 bit 7 654321 bit 0 read: por pin cop ilop ilad 0 lvi 0 write: rrrrrrrr reset: 1 x 0000x0 r = reserved x = indeterminate figure 9-18. sim reset status register (srsr)
system integration module (sim) sim registers MC68HC708AS48 rev. 4.0 advance information motorola system integration module (sim) 147 non-disclosure agreement required ilad illegal address reset flag 1 = illegal address reset since last read of rsr 0 = power-on reset or read of rsr since last illegal address reset lvi low-voltage inhibit reset flag 1 = lvi reset since last read of rsr 0 = power-on reset or read of rsr since last lvi reset 9.8.3 sim break flag control register the sim break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe break clear flag enable bit in some module registers, this read/write bit will enable software to clear status bits by accessing status registers only while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set.this operation is important for modules with status bits which can be cleared only by being read. see the register descriptions in each module for additional details. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7 654321 bit 0 read: bcfe rrrrrrr write: reset: 0 r = reserved figure 9-19. sim break flag control register (sbfcr)
non-disclosure agreement required system integration module (sim) advance information MC68HC708AS48 rev. 4.0 148 system integration module (sim) motorola
MC68HC708AS48 rev. 4.0 advance information motorola low-voltage inhibit (lvi) 149 non-disclosure agreement required advance information MC68HC708AS48 section 10. low-voltage inhibit (lvi) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 10.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 10.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 10.2 introduction this section describes the low-voltage inhibit module (lvi), which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 10.3 features features of the lvi module include: ? programmable lvi reset ? programmable power consumption
non-disclosure agreement required low-voltage inhibit (lvi) advance information MC68HC708AS48 rev. 4.0 150 low-voltage inhibit (lvi) motorola 10.4 functional description figure 10-1 shows the structure of the lvi module. the lvi module contains a bandgap reference circuit and comparator. the lvi power disable bit, lvipwrd, disables the lvi from monitoring v dd voltage. the lvi reset disable bit, lvirstd, disables the lvi module from generating a reset when v dd falls below a voltage, v lvii . lvipwrd and lvirstd are in the config register ($001f) (see 5.4 configuration register ). once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v lvir . the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 10-1. lvi module block diagram low v dd lvirstd lviout lvipwrd detector v dd lvi reset from config lvistop from config stop instruction
low-voltage inhibit (lvi) functional description MC68HC708AS48 rev. 4.0 advance information motorola low-voltage inhibit (lvi) 151 non-disclosure agreement required 10.4.1 polled lvi operation in applications that can operate at v dd levels below the v lvii level, software can monitor v dd by polling the lviout bit. in the config register, the lvipwrd bit must be at logic 0 to enable the lvi module, and the lvirstd bit must be at logic 1 to disable lvi resets. 10.4.2 forced reset operation in applications that require v dd to remain above the v lvii level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the v lvii level. in the config register, the lvipwrd and lvirstd bits must be at logic 0 to enable the lvi module and to enable lvi resets. addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe0f lvi status register (lvisr) read: lviout 0 0 0 lvistop lvilck 00 write: r r r r r r reset: 0 0 0 0 0 0 0 0 r = reserved figure 10-2. lvi i/o register summary
non-disclosure agreement required low-voltage inhibit (lvi) advance information MC68HC708AS48 rev. 4.0 152 low-voltage inhibit (lvi) motorola 10.5 lvi status register the lvi status register flags v dd voltages below the v lvii level. lvilck lvi lock bit this read/write bit inhibits writing to the lvi status and control register. when lvilck is set, writing to the lvi status and control register has no effect. the lvilck bit can be cleared only by reset. 1 = lviscr write-protected 0 = lviscr not write-protected lvistop lvi disable in stop mode bit this read/write bit turns off the low-voltage inhibit module (lvi) in stop mode when clear. 1 = lvi not disabled during stop mode 0 = lvi disabled during stop mode note: to meet the stop mode i dd specification, lvistop must be at logic 0. lviout lvi output bit this read-only flag becomes set when the v dd voltage falls below the v lvii voltage. (see table 10-1 .) reset clears the lviout bit. address: $fe0f bit 7 654321 bit 0 read: lviout 0 0 0 lvistop lvilck 00 write: rrrr rr reset: 00000000 r = reserved figure 10-3. lvi status register (lvisr) table 10-1. lviout bit indication v dd lviout v dd > v lvir 0 v dd < v lvii 1 v lvii < v dd < v lvir previous value
low-voltage inhibit (lvi) lvi interrupts MC68HC708AS48 rev. 4.0 advance information motorola low-voltage inhibit (lvi) 153 non-disclosure agreement required 10.6 lvi interrupts the lvi module does not generate interrupt requests. 10.7 low-power modes the stop and wait instructions put the mcu in low-power standby modes. 10.7.1 wait mode with the lvipwrd bit in the config register programmed to logic 0, the lvi module is active after a wait instruction. with the lvirstd bit in the config register programmed to logic 0, the lvi module can generate a reset and bring the mcu out of wait mode. 10.7.2 stop mode when the lvipwrd bit in the config register is programmed to logic 0 and the lvistop bit in the lvisr register is at logic 1, the lvi module remains active after a stop instruction. note: if the lvipwrd bit is at logic 0, the lvistop bit must be at logic 0 to meet the minimum stop mode i dd specification.
non-disclosure agreement required low-voltage inhibit (lvi) advance information MC68HC708AS48 rev. 4.0 154 low-voltage inhibit (lvi) motorola
MC68HC708AS48 rev. 4.0 advance information motorola break module (break) 155 non-disclosure agreement required advance information MC68HC708AS48 section 11. break module (break) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 11.4.1 flag protection during break interrupts . . . . . . . . . . . . . .157 11.4.2 cpu during break interrupts. . . . . . . . . . . . . . . . . . . . . . .158 11.4.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . .158 11.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . .158 11.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 11.5.1 break status and control register . . . . . . . . . . . . . . . . . .159 11.5.2 break address registers. . . . . . . . . . . . . . . . . . . . . . . . . .160 11.6 wait or stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.2 introduction this section describes the break module (break). the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
non-disclosure agreement required break module (break) advance information MC68HC708AS48 rev. 4.0 156 break module (break) motorola 11.3 features features of the break module include: ? accessible i/o registers during the break interrupt ? cpu-generated break interrupts ? software-generated break interrupts ? cop disabling during break interrupts 11.4 functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal ( bkpt) to the sim. the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: ? a cpu-generated address (the address in the program counter) matches the contents of the break address registers ? software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 11-1 shows the structure of the break module.
break module (break) functional description MC68HC708AS48 rev. 4.0 advance information motorola break module (break) 157 non-disclosure agreement required figure 11-1. break module block diagram 11.4.1 flag protection during break interrupts the system integration module (sim) controls whether module status bits can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 9.8.3 sim break flag control register and the break interrupts subsection for each module.) addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe0c break address register high (brkh) see page 160. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $fe0d break address register low (brkl) see page 160. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $fe0e break status and control register (brkscr) see page 159. read: brke brka 000000 write: r r r r r r reset: 0 0 0 0 0 0 0 0 r = reserved figure 11-2. break i/o register summary iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt to sim
non-disclosure agreement required break module (break) advance information MC68HC708AS48 rev. 4.0 158 break module (break) motorola 11.4.2 cpu during break interrupts the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffcC$fffd ($fefcC$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 11.4.3 tim during break interrupts a break interrupt stops the timer counter. 11.4.4 cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. for v hi see 21.5 5.0 volt dc electrical characteristics . 11.5 break module registers three registers control and monitor operation of the break module: ? break status and control register, brkscr ? break address register high, brkh ? break address register low, brkl
break module (break) break module registers MC68HC708AS48 rev. 4.0 advance information motorola break module (break) 159 non-disclosure agreement required 11.5.1 break status and control register the break status and control register contains break module enable and status bits. brke break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0e bit 7 654321 bit 0 read: brke brka 000000 write: rrrrrr reset: 00000000 r = reserved figure 11-3. break status and control register (brkscr)
non-disclosure agreement required break module (break) advance information MC68HC708AS48 rev. 4.0 160 break module (break) motorola 11.5.2 break address registers the break address registers contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 11.6 wait or stop mode the wait and stop instructions put the mcu in low-power standby modes. a break interrupt causes exit from wait or stop mode and sets the sbsw bit in the sim break status register (see 9.8 sim registers ). address: $fe0c bit 7 654321 bit 0 read: bit 15 bit 13 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 00000000 figure 11-4. break address register (brkh) address: $fe0d bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 00000000 figure 11-5. break address register (brkl)
MC68HC708AS48 rev. 4.0 advance information motorola monitor rom (mon) 161 non-disclosure agreement required advance information MC68HC708AS48 section 12. monitor rom (mon) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 12.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . .164 12.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 12.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 12.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 12.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 12.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 12.2 introduction this section describes the monitor rom (mon). the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer.
non-disclosure agreement required monitor rom (mon) advance information MC68HC708AS48 rev. 4.0 162 monitor rom (mon) motorola 12.3 features features of the monitor rom include: ? normal user-mode pin functionality ? one pin dedicated to serial communication between monitor rom and host computer ? standard mark/space non-return-to-zero (nrz) communication with host computer ? 4800 baudC28.8 kbaud communication with host computer ? execution of code in ram or eprom/otprom ? (e)eprom/otprom programming 12.4 functional description monitor rom receives and executes commands from a host computer. figure 12-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the MC68HC708AS48 has an eprom/otprom security feature that requires proper procedures to be followed before the eprom/otprom can be accessed. therefore, access to the eprom/otprom is denied to unauthorized users of customer specified software. in monitor mode, the mcu can execute host-computer code in ram while all mcu pins except pta0 retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor.
monitor rom (mon) functional description MC68HC708AS48 rev. 4.0 advance information motorola monitor rom (mon) 163 non-disclosure agreement required figure 12-1. monitor mode circuit + + + 10 m w x1 v dd v dda v dd + v hi mc145407 mc74hc125 68hc08 rst irq1/v pp v dda /v ddaref cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k w 0.1 m f 0.1 m f 10 w 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 m f 10 m f 10 m f 10 m f 1 2 4 7 14 3 0.1 m f 4.9152 mhz 10 k w ptc3 v dd 10 k w b a note: position a bus clock = cgmxclk ? 4 or cgmvclk ? 4 position b bus clock = cgmxclk ? 2 (see note.) 5 6 + ptc0 ptc1 v dd 10 k w
non-disclosure agreement required monitor rom (mon) advance information MC68HC708AS48 rev. 4.0 164 monitor rom (mon) motorola 12.4.1 entering monitor mode table 12-1 shows the pin conditions for entering monitor mode. enter monitor mode by either ? executing a software interrupt instruction (swi) or ? applying a logic 0 and then a logic 1 to the rst pin. the mcu sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the necessary baud rate. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v dd +v hi (see 21.5 5.0 volt dc electrical characteristics ) is applied to either the irq/v pp pin or the v dd pin. (see section 9. system integration module (sim) for more information on modes of operation.) note: holding the ptc3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 12-1. mode selection irq/v pp pin ptc0 pin ptc1 pin pta0 pin ptc3 pin mode cgmout bus frequency v dd + v hi (1) 1 0 1 1 monitor or v dd + v hi (1) 1 0 1 0 monitor cgmxclk 1. for v hi see 21.5 5.0 volt dc electrical characteristics and 21.2 maximum ratings cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 --------------------------
monitor rom (mon) functional description MC68HC708AS48 rev. 4.0 advance information motorola monitor rom (mon) 165 non-disclosure agreement required table 12-2 is a summary of the differences between user mode and monitor mode. 12.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 12-2 and figure 12-3 .) the data transmit and receive rate can be anywhere from 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. figure 12-2. monitor data format figure 12-3. sample monitor waveforms table 12-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v dd + v hi ) is removed from the irq/v pp pin while in monitor mode, the sim asserts its cop enable output. the cop is an option enabled or disabled by the copd bit in the configuration register. (see 21.5 5.0 volt dc electrical characteristics .) $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7
non-disclosure agreement required monitor rom (mon) advance information MC68HC708AS48 rev. 4.0 166 monitor rom (mon) motorola 12.4.3 echoing as shown in figure 12-4 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. any result of a command appears after the echo of the last byte of the command. figure 12-4. read transaction 12.4.4 break signal a start bit followed by nine low bits is a break signal. (see figure 12-5 .) when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. figure 12-5. break transaction addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo
monitor rom (mon) functional description MC68HC708AS48 rev. 4.0 advance information motorola monitor rom (mon) 167 non-disclosure agreement required 12.4.5 commands the monitor rom uses these commands: ? read, read memory ? write, write memory ? iread, indexed read ? iwrite, indexed write ? readsp, read stack pointer ? run, run user program a sequence of iread or iwrite commands can access a block of memory sequentially over the full 64-kbyte memory map. table 12-3. read (read memory) command description read byte from memory operand speci?es 2-byte address in high byte:low byte order data returned returns contents of speci?ed address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result
non-disclosure agreement required monitor rom (mon) advance information MC68HC708AS48 rev. 4.0 168 monitor rom (mon) motorola table 12-4. write (write memory) command description write byte to memory operand speci?es 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data table 12-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand speci?es 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result
monitor rom (mon) functional description MC68HC708AS48 rev. 4.0 advance information motorola monitor rom (mon) 169 non-disclosure agreement required table 12-6. iwrite (indexed write) command description write to last address accessed + 1 operand speci?es single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor table 12-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result
non-disclosure agreement required monitor rom (mon) advance information MC68HC708AS48 rev. 4.0 170 monitor rom (mon) motorola 12.4.6 baud rate with a 4.9152-mhz crystal and the ptc3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by the mul[7:4] bits in the pll programming register (ppg). (see section 8. clock generator module (cgm) .) table 12-8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 12-9. monitor baud rate selection vco frequency multiplier (n) 123456 monitor baud rate (4.9152 mhz) 4800 9600 14,400 19,200 24,000 28,800 monitor baud rate (4.194 mhz) 4096 8192 12,288 16,384 20,480 24,576
MC68HC708AS48 rev. 4.0 advance information motorola computer operating properly (cop) 171 non-disclosure agreement required advance information MC68HC708AS48 section 13. computer operating properly (cop) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 13.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.1 cgmxclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.4 internal reset resources . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.7 copl (cop long timeout) . . . . . . . . . . . . . . . . . . . . . . .175 13.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.9 cop module during break interrupts . . . . . . . . . . . . . . . . . . .176 13.2 introduction this section describes the computer operating properly (cop) module, a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by periodically clearing the cop counter.
non-disclosure agreement required computer operating properly (cop) advance information MC68HC708AS48 rev. 4.0 172 computer operating properly (cop) motorola 13.3 functional description figure 13-1 shows the structure of the cop module. figure 13-1. cop block diagram addr. register name bit 7 6 5 4 3 2 1 bit 0 $ffff cop control register (copctl) read: low byte of reset vector write: writing to $ffff clears cop counter reset: unaffected by reset figure 13-2. cop i/o register summary copctl write cgmxclk reset vector fetch sim reset circuit sim reset status register internal reset sources (1) stop instruction sim clear bits 12C4 12-bit sim counter clear all bits 6-bit cop counter copd (from config) reset copctl write clear cop module copen (from sim) cop counter note: 1. see 9.4.2 active resets from internal sources . copl
computer operating properly (cop) functional description MC68HC708AS48 rev. 4.0 advance information motorola computer operating properly (cop) 173 non-disclosure agreement required the cop counter is a free-running 6-bit counter preceded by the 12-bit system integration module (sim) counter. cop timeouts are determined strictly by the cgm crystal oscillator clock signal (cgmxclk), not the cgmout signal (see figure 8-1. cgm block diagram ). if not cleared by software, the cop counter overflows and generates an asynchronous reset after 8,176 or 262,128 cgmxclk cycles, depending upon copl bit in the config register ($001f) (see 5.4 configuration register .) cop timeout period = 8,176 or 262,128 / f osc with a 4.9152-mhz crystal and the copl bit in the config register ($001f) set to a logic 1, the cop timeout period is approximately 53.3 ms. writing any value to location $ffff before overflow occurs clears the cop counter, clears bits 12 through 4 of the sim counter, and prevents reset. a cpu interrupt routine can be used to clear the cop. note: the cop should be serviced as soon as possible out of reset and before entering or after exiting stop mode to guarantee the maximum selected amount of time before the first timeout. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the sim reset status register (srsr) (see 9.8.2 reset status register ). while the microcontroller is in monitor mode, the cop module is disabled if the rst pin or the irq/v pp pin is held at v dd +v hi (see 21.5 5.0 volt dc electrical characteristics ). during a break state, v dd + v hi on the rst pin disables the cop module. note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly.
non-disclosure agreement required computer operating properly (cop) advance information MC68HC708AS48 rev. 4.0 174 computer operating properly (cop) motorola 13.4 i/o signals the following paragraphs describe the signals shown in figure 13-1 . 13.4.1 cgmxclk cgmxclk is the crystal oscillator output signal. cgmxclk frequency is equal to the crystal frequency. 13.4.2 stop instruction the stop instruction clears the sim counter. 13.4.3 copctl write writing any value to the cop control register (copctl) (see 13.5 cop control register ) clears the cop counter and clears bits 12 through 4 of the sim counter. reading the cop control register returns the reset vector. 13.4.4 internal reset resources an internal reset clears the sim counter and the cop counter. (see 9.4.2 active resets from internal sources .) 13.4.5 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the sim counter. 13.4.6 copd (cop disable) the copd bit reflects the state of the cop disable bit (copd) in the config register ($001f).this signal disables cop generated resets when asserted. (see 5.4 configuration register .)
computer operating properly (cop) cop control register MC68HC708AS48 rev. 4.0 advance information motorola computer operating properly (cop) 175 non-disclosure agreement required 13.4.7 copl (cop long timeout) the copl bit selects the state of the cop long timeout bit (copl) in the config register ($001f). timeout periods can be 8,176 or 262,128 cgmxclk cycles. (see 5.4 configuration register .) 13.5 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 13.6 interrupts the cop does not generate cpu interrupt requests. 13.7 monitor mode the cop is disabled in monitor mode when v dd +v hi (see 21.5 5.0 volt dc electrical characteristics ) is present on the irq/v pp pin or on the rst pin. address: $ffff bit 7 654321 bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 13-3. cop control register (copctl)
non-disclosure agreement required computer operating properly (cop) advance information MC68HC708AS48 rev. 4.0 176 computer operating properly (cop) motorola 13.8 low-power modes the following subsections describe the low-power modes. 13.8.1 wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. note: if the cop is enabled in wait mode, it must be periodically refreshed. 13.8.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the config register ($001f) (see 5.4 configuration register ) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by programming the stop bit to logic 0. 13.9 cop module during break interrupts the cop is disabled during a break interrupt when v dd +v hi (see 21.5 5.0 volt dc electrical characteristics ) is present on the rst pin.
MC68HC708AS48 rev. 4.0 advance information motorola external interrupt 177 non-disclosure agreement required advance information MC68HC708AS48 section 14. external interrupt 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 14.5 irq/v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 14.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . .182 14.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . .182 14.2 introduction this section describes the non-maskable external interrupt ( irq/v pp ) input. 14.3 features features include: ? dedicated external interrupt pin ( irq/v pp ) ? hysteresis buffer ? programmable edge-only or edge and level interrupt sensitivity ? automatic interrupt acknowledge
non-disclosure agreement required external interrupt advance information MC68HC708AS48 rev. 4.0 178 external interrupt motorola 14.4 functional description a logic 0 applied to the external interrupt pin can latch a cpu interrupt request. figure 14-1 shows the structure of the irq module. interrupt signals on the irq/v pp pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: ? vector fetch a vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. ? software clear software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack bit clears the irq latch. ? reset a reset automatically clears both interrupt latches. figure 14-1. irq block diagram ack imask dq ck clr irq high interrupt to mode select logic irq latch request irq/v pp v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus
external interrupt functional description MC68HC708AS48 rev. 4.0 advance information motorola external interrupt 179 non-disclosure agreement required the external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge and low-level triggered. the mode bit in the iscr controls the triggering sensitivity of the irq/v pp pin. when an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: ? vector fetch or software clear ? return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the iscr masks all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the corresponding imask bit is clear. note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. (see figure 14-3 .) addr. register name bit 7 6 5 4 3 2 1 bit 0 $001a irq status and control register (iscr) see page 183. read: 0 0 0 0 irqf 0 imask mode write: r r r r r ack reset: 0 0 0 0 0 0 0 0 r = reserved figure 14-2. irq i/o register summary
non-disclosure agreement required external interrupt advance information MC68HC708AS48 rev. 4.0 180 external interrupt motorola figure 14-3. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction. swi instruction? rti instruction? no stack cpu registers. no set i bit. load pc with interrupt vector. no yes unstack cpu registers. execute instruction. yes yes
external interrupt irq/vpp pin MC68HC708AS48 rev. 4.0 advance information motorola external interrupt 181 non-disclosure agreement required 1 4. 5 irq/ vpp pin a logi c 0 o n the irq/v pp pi n ca n latc h a n interrup t reques t int o th e irq latch. a vector fetch, software clear, or reset clears the irq latch. i f th e mod e bi t i s set , the irq/v pp pi n i s bot h falling-edg e sensitiv e and low-level sensitive. with mode set, both of the following actions must occur to clear the irq latch: ? vector fetch or software clear a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic 1 to th e ac k bi t i n th e interrup t statu s an d contro l registe r (iscr) . the ack bit is useful in applications that poll the irq/v pp pin and requir e softwar e t o clea r th e ir q latch . writin g t o th e ac k bi t can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq/v pp pin. a falling edge on irq/v pp that occurs after writing to the ack bit latches anothe r interrup t request . i f th e ir q mas k bit , imask , i s clear , the cpu loads the program counter with the vector address at locations $fffa and $fffb. ? retur n o f the irq/v pp pi n t o logi c 1 a s lon g a s the irq/v pp pin is at logic 0, the irq latch remains set. the vector fetch or software clear and the return of the irq/v pp pin to logi c 1 ca n occu r i n an y order . th e interrup t reques t remain s pendin g as lon g a s the irq/v pp pi n i s a t logi c 0 . a rese t wil l clea r th e latc h an d the mod e contro l bit , thereb y clearin g th e interrup t eve n i f th e pi n stay s low. if the mode bit is clear, the irq/v pp pin is falling-edge sensitive only. wit h mod e clear , a vecto r fetc h o r softwar e clea r immediatel y clear s the irq latch.
non-disclosure agreement required external interrupt advance information MC68HC708AS48 rev. 4.0 182 external interrupt motorola the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq/v pp pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 14.6 irq module during break interrupts the system integration module (sim) controls whether the irq interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latches during the break state. (see 9.8.3 sim break flag control register .) to allow software to clear the irq latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 14.7 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has these functions: ? shows the state of the irq interrupt flag ? clears the irq interrupt latch ? masks irq interrupt request ? controls triggering sensitivity of the irq/v pp interrupt pin
external interrupt irq status and control register MC68HC708AS48 rev. 4.0 advance information motorola external interrupt 183 non-disclosure agreement required irqf irq/v pp flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq/v pp interrupt pending 0 = irq/v pp interrupt not pending ack irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask irq/v pp interrupt mask bit writing a logic 1 to this read/write bit disables irq/v pp interrupt requests. reset clears imask. 1 = irq/v pp interrupt requests disabled 0 = irq/v pp interrupt requests enabled mode irq/v pp edge/level select bit this read/write bit controls the triggering sensitivity of the irq/v pp pin. reset clears mode. 1 = irq/v pp interrupt requests on falling edges and low levels 0 = irq/v pp interrupt requests on falling edges only address: $001a bit 7 654321 bit 0 read: 0000 irqf 0 imask mode write: rrrrrack reset: 00000000 r = reserved figure 14-4. irq status and control register (iscr)
non-disclosure agreement required external interrupt advance information MC68HC708AS48 rev. 4.0 184 external interrupt motorola
MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 185 non-disclosure agreement required advance information MC68HC708AS48 section 15. input/output (i/o) ports 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 15.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 15.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 15.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . .189 15.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 15.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 15.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . .192 15.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 15.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 15.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . .195 15.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 15.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 15.6.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . .199 15.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 15.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 15.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . .203 15.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 15.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 15.8.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . .206 15.9 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 15.9.1 port g data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 15.9.2 data direction register g . . . . . . . . . . . . . . . . . . . . . . . . .209
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 186 input/output (i/o) ports motorola 15.2 introduction in the 52-plcc package (MC68HC708AS48cfn), thirty-nine bidirectional input/output (i/o) pins and one input-only pin form six parallel ports. in the 64-qfp package (engineering samples), forty-five bidirectional i/o pins and one input only pin form seven parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 188. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 191. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 194. read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r reset: unaffected by reset $0003 port d data register (ptd) see page 197. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 189. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 r = reserved figure 15-1. i/o port register summary
input/output (i/o) ports introduction MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 187 non-disclosure agreement required $0005 data direction register b (ddrb) see page 192. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) see page 195. read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset: 0 0 0 0 0 0 0 0 $0007 data direction register d (ddrd) see page 199. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 0 ddrd1 ddrd0 write: r reset: 0 0 0 0 0 0 0 0 $0008 port e data register (pte) see page 201. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 205. read: 0 0 0 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r r reset: unaffected by reset $000a port g data register (ptg) see page 208. read: 0 0 0 0 0 ptg2 ptg1 ptg0 write: r r r r r reset: unaffected by reset $000c data direction register e (ddre) see page 203. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 $000d data direction register f (ddrf) see page 206. read: 0 0 0 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r r reset: 0 0 0 0 0 0 0 0 $000e data direction register g (ddrg) see page 209. read: 0 0 0 0 0 ddrg2 ddrg1 ddrg0 write: r r r r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved figure 15-1. i/o port register summary (continued)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 188 input/output (i/o) ports motorola 15.3 port a port a is an 8-bit, general-purpose, bidirectional i/o port. 15.3.1 port a data register the port a data register contains a data latch for each of the eight port a pins. pta[7:0] port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. address: $0000 bit 7 654321 bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 15-2. port a data register (pta)
input/output (i/o) ports port a MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 189 non-disclosure agreement required 15.3.2 data direction register a data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 15-4 shows the port a i/o logic. figure 15-4. port a i/o circuit address: $0004 bit 7 654321 bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 figure 15-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 190 input/output (i/o) ports motorola when bit ddrax is a logic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-1 summarizes the operation of the port a pins. table 15-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x input, hi-z ddra[7:0] pin pta[7:0] (1) 1 x output ddra[7:0] pta[7:0] pta[7:0] x = dont care hi-z = high impedance 1. writing affects data register, but does not affect input.
input/output (i/o) ports port b MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 191 non-disclosure agreement required 15.4 port b port b is an 8-bit special function port that shares all of its pins with the analog-to-digital converter (adc). 15.4.1 port b data register the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. atd[7:0] adc channels ptb7/atd7Cptb0/atd0 are eight of the analog-to-digital converter channels. the adc channel select bits, ch[4:0], determine whether the ptb7/atd7Cptb0/atd0 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. (see section 19. analog-to-digital converter (adc) .) data direction register b (ddrb) does not affect the data direction of port b pins that are being used by the adc. however, the ddrb bits always determine whether reading port b returns to the states of the latches or logic 0. address: $0001 bit 7 654321 bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate functions: atd7 atd6 atd5 atd4 atd3 atd2 atd1 atd0 figure 15-5. port b data register (ptb)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 192 input/output (i/o) ports motorola 15.4.2 data direction register b data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb[7:0] data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 15-7 shows the port b i/o logic. figure 15-7. port b i/o circuit address: $0005 bit 7 654321 bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 figure 15-6. data direction register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
input/output (i/o) ports port b MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 193 non-disclosure agreement required when bit ddrbx is a logic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin, or a logic 0 if that particular bit is in use by the adc. the data latch can always be written, regardless of the state of its data direction bit. table 15-2 summarizes the operation of the port b pins. table 15-2. port b pin functions ddrb bit ptb bit bit selected by adc i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x no input, hi-z ddrb[7:0] pin ptb[7:0] (1) 1 x no output ddrb[7:0] ptb[7:0] ptb[7:0] 0 x yes input, hi-z ddrb[7:0] 0 ptb[7:0] (1) 1 x yes input, hi-z ddrb[7:0] ptb[7:0] ptb[7:0] x = dont care hi-z = high impedance 1. writing affects data register, but does not affect input.
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 194 input/output (i/o) ports motorola 15.5 port c port c is a 6-bit, general-purpose, bidirectional i/o port that shares one of its pins with the bus clock (mclk). 15.5.1 port c data register the port c data register contains a data latch for each of the six port c pins. ptc[5:0] port c data bits these read/write bits are software-programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. note: ptc5 is available only in the 64-pin qfp package. mclk t12 system bus clock bit the bus clock (mclk) is driven out of ptc2 when enabled by the mclken bit in ptcddr7. address: $0002 bit 7 654321 bit 0 read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r reset: unaffected by reset r = reserved alternate functions: mclk figure 15-8. port c data register (ptc)
input/output (i/o) ports port c MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 195 non-disclosure agreement required 15.5.2 data direction register c data direction register c determines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. mclken mclk enable bit this read/write bit enables mclk to be an output signal on ptc2. if mclk is enabled, ptc2 is under the control of mclken. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled ddrc[5:0] data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. note: ddrc is available only in the 64-pin qfp package. figure 15-10 shows the port c i/o logic. address: $0006 bit 7 654321 bit 0 read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset: 00000000 r = reserved figure 15-9. data direction register c (ddrc)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 196 input/output (i/o) ports motorola figure 15-10. port c i/o circuit when bit ddrcx is a logic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-3 summarizes the operation of the port c pins. table 15-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write [7] = 0 ptc2 input, hi-z ddrc[7] 0 ptc2 [7] = 1 ptc2 output, mclk ddrc[7] data latch 0 x input, hi-z ddrc[5:0] pin ptc[5:3, 1:0] (1) 1 x output ddrc[5:0] ptc[5:0] ptc[5:3, 1:0] x = dont care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus
input/output (i/o) ports port d MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 197 non-disclosure agreement required 15.6 port d port d is an 8-bit special function i/o port that shares all of its pins with the analog-to-digital converter (adc). note: ptd2/atd10 is an input-only port pin 15.6.1 port d data register the port d data register contains a data latch for seven of the eight port d pins. writes to ptd2 are not latched since it is an input-only port bit. ptd[7:3, 1:0] port d data bits ptd[7:3, 1:0] are read/write, software programmable bits. data direction of ptd[7:3, 1:0] pins are under the control of the corresponding bit in data direction register d. atd[15:8] adc channel status bits ptd7/atd15Cptd0/atd8 are eight of the analog-to-digital converter channels. the adc channel select bits, ch[4:0], determine whether the ptd7/atd15Cptd0/atd8 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will address: $0003 bit 7 654321 bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r reset: unaffected by reset alternate functions: atd15 atd14/ tclk atd13 atd12 atd11 atd10 atd9 atd8 r = reserved figure 15-11. port d data register (ptd)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 198 input/output (i/o) ports motorola be 0 if the data direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. (see section 19. analog-to-digital converter (adc) .) note: ptd7/atd15 is available only in the 64-pin qfp package data direction register d (ddrd) does not affect the data direction of port d pins that are being used by the adc. however, the ddrd bits always determine whether reading port d returns the states of the latches or logic 0. tclk timer clock input bit the ptd6/atd14/tclk pin is the external clock input for the tim. the prescaler select bits, ps[2:0], select ptd6/atd14/tclk as the tim clock input. (see 16.9.1 tim status and control register .) when not selected as the tim clock, ptd6/atd14/tclk is available for general-purpose i/o or as an adc channel. note: do not use adc channel atd14 when using the ptd6/atd14/tclk pin as the clock input for the tim.
input/output (i/o) ports port d MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 199 non-disclosure agreement required 15.6.2 data direction register d data direction register d determines whether each port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. ddrd[7:3, 1:0] data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:3, 1:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. note: ddrd7 is available only in the 64-pin qfp package. figure 15-13 shows the port d i/o logic ptd[7:3, 1:0]. address: $0007 bit 7 654321 bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 0 ddrd1 ddrd0 write: r reset: 00000000 r = reserved figure 15-12. data direction register d (ddrd)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 200 input/output (i/o) ports motorola figure 15-13. port d i/o circuit when bit ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-4 summarizes the operation of the port d pins. read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus table 15-4. port d pin functions ddrd bit ptd bit bit selected by adc i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x no input, hi-z ddrd[7:3, 1:0] pin ptd[7:3, 1:0] (1) 1 x no output ddrd[7:3, 1:0] ptd[7:3, 1:0] ptd[7:3, 1:0] 0 x yes input, hi-z ddrd[7:3, 1:0] 0 ptd[7:3, 1:0] (1) 1 x yes input, hi-z ddrd[7:3, 1:0] ptd[7:3, 1:0] ptd[7:3, 1:0] x = dont care hi-z = high impedance 1. writing affects data register, but does not affect input.
input/output (i/o) ports port e MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 201 non-disclosure agreement required 15.7 port e port e is an 8-bit special function port that shares two of its pins with the timer interface module (tim), two of its pins with the serial communications interface module (sci), and four of its pins with the serial peripheral interface module (spi). 15.7.1 port e data register the port e data register contains a data latch for each of the eight port e pins. pte[7:0] port e data bits pte[7:0] are read/write, software programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. spsck spi serial clock bit the pte7/spsck pin is the serial clock input of an spi slave module and serial clock output of an spi master module. when the spe bit is clear, the pte7/spsck pin is available for general-purpose i/o. mosi master out/slave in bit the pte6/mosi pin is the master out/slave in terminal of the spi module. when the spe bit is clear, the pte6/mosi pin is available for general-purpose i/o. (see 18.14.1 spi control register .) address: $0008 bit 7 654321 bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternate function: spsck mosi miso ss tch1 tch0 rxd txd figure 15-14. port e data register (pte)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 202 input/output (i/o) ports motorola miso master in/slave out bit the pte5/miso pin is the master in/slave out terminal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pte5/miso pin is available for general-purpose i/o. (see 18.14.1 spi control register .) ss slave select bit the pte4/ ss pin is the slave select input of the spi module. when the spe bit is clear, or when the spi master bit, spmstr, is set and modfen bit is low, the pte4/ ss pin is available for general-purpose i/o. (see 18.13.4 ss (slave select) .) when the spi is enabled as a slave, the ddre4 bit in data direction register e (ddre) has no effect on the pte4/ ss pin. note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the spi module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 15-5 .) tch[1:0] timer channel i/o bits the pte3/tch1Cpte2/tch0 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the pte3/tch1Cpte2/tch0 pins are timer channel i/o pins or general-purpose i/o pins. (see 16.9.4 tim channel status and control registers .) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 15-5 .) rxd sci receive data input bit the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. (see 17.9.1 sci control register 1 .)
input/output (i/o) ports port e MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 203 non-disclosure agreement required txd sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. (see 17.9.1 sci control register 1 .) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 15-5 .) 15.7.2 data direction register e data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[7:0] data direction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 15-16 shows the port e i/o logic. address: $000c bit 7 654321 bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 figure 15-15. data direction register e (ddre)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 204 input/output (i/o) ports motorola figure 15-16. port e i/o circuit when bit ddrex is a logic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-5 summarizes the operation of the port e pins. table 15-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x input, hi-z ddre[7:0] pin pte[7:0] (1) 1 x output ddre[7:0] pte[7:0] pte[7:0] x = dont care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
input/output (i/o) ports port f MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 205 non-disclosure agreement required 15.8 port f port f is a 5-bit special function port that shares four of its pins with the timer interface module (tim). 15.8.1 port f data register the port f data register contains a data latch for each of the five port f pins. ptf[4:0] port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the corresponding bit in data direction register f. reset has no effect on ptf[4:0]. note: ptf4 is available only in the 64-pin qfp package. tch[5:2] timer channel i/o bits the ptf3/tch5Cptf0/tch2 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf3/tch5Cptf0/tch2 pins are timer channel i/o pins or general-purpose i/o pins. (see 16.9.4 tim channel status and control registers .) note: data direction register f (ddrf) does not affect the data direction of port f pins that are being used by the tim. however, the ddrf bits always address: $0009 bit 7 654321 bit 0 read: 0 0 0 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r r reset: unaffected by reset alternate function: tch5 tch4 tch3 tch2 r = reserved figure 15-17. port f data register (ptf)
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 206 input/output (i/o) ports motorola determine whether reading port f returns the states of the latches or the states of the pins. (see table 15-6 .) 15.8.2 data direction register f data direction register f determines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a logic 0 disables the output buffer. ddrf[4:0] data direction register f bits these read/write bits control port f data direction. reset clears ddrf[4:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note: ddrf4 is available only in the 64-pin qfp package. note: avoid glitches on port f pins by writing to the port f data register before changing data direction register f bits from 0 to 1. figure 15-19 shows the port f i/o logic. address: $000d bit 7 654321 bit 0 read: 0 0 0 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r r reset: 00000000 r = reserved figure 15-18. data direction register f (ddrf)
input/output (i/o) ports port f MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 207 non-disclosure agreement required figure 15-19. port f i/o circuit when bit ddrfx is a logic 1, reading address $0009 reads the ptfx data latch. when bit ddrfx is a logic 0, reading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-6 summarizes the operation of the port f pins. table 15-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x input, hi-z ddrf[4:0] pin ptf[4:0] (1) 1 x output ddrf[4:0] ptf[3:0] ptf[4:0] x = dont care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus
non-disclosure agreement required input/output (i/o) ports advance information MC68HC708AS48 rev. 4.0 208 input/output (i/o) ports motorola 15.9 port g port g is a 3-bit general-purpose i/o port. note: port g is available only in the 64-pin qfp package 15.9.1 port g data register the port g data register contains a data latch for each of the three port g pins. ptg[2:0] port g data bits these read/write bits are software programmable. data direction of each port g pin is under the control of the corresponding bit in data direction register g. reset has no effect on ptg [2:0]. address: $000a bit 7 654321 bit 0 read: 00000 ptg2 ptg1 ptg0 write: rrrrr reset: unaffected by reset r = reserved figure 15-20. port g data register (ptg)
input/output (i/o) ports port g MC68HC708AS48 rev. 4.0 advance information motorola input/output (i/o) ports 209 non-disclosure agreement required 15.9.2 data direction register g data direction register g determines whether each port g pin is an input or an output. writing a logic 1 to a ddrg bit enables the output buffer for the corresponding port g pin; a logic 0 disables the output buffer. ddrg[2:0] data direction register g bits these read/write bits control port g data direction. reset clears ddrg[2:0], configuring all port g pins as inputs. 1 = corresponding port g pin configured as output 0 = corresponding port g pin configured as input note: avoid glitches on port g pins by writing to the port g data register before changing data direction register g bits from 0 to 1. figure 15-19 shows the port g i/o logic. figure 15-22. port g i/o circuit address: $000e bit 7 654321 bit 0 read: 00000 ddrg2 ddrg1 ddrg0 write: rrrrr reset: 00000000 r = reserved figure 15-21. data direction register g (ddrg) read ddrg ($000e) write ddrg ($000e) reset write ptg ($000a) read ptg ($000a) ptgx ddrgx ptgx internal data bus
non-disclosure agreement required input/output (i/o) p o r t s advance information MC68HC708AS48 rev. 4.0 210 input/output (i/o) ports motorola when bit ddrgx is a logic 1, reading address $000a reads the ptgx dat a latch . whe n bi t ddrg x i s a logi c 0 , readin g addres s $000 a reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit . table 15-7 summarizes the operation of the port g pins. t a ble 15-7. p o r t g pin functions ddrg bit ptg bit i/o pin mode accesses to ddrg accesses to ptg read/write read write 0 x input, hi-z ddrg[2:0] pin ptg[2:0] (1) 1 x output ddrg[2:0] ptg[2:0] ptg[2:0] x = dont care hi-z = high impedance 1 . w r iting af f ects data registe r , b ut does not af f ect input.
MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 211 non-disclosure agreement required advance information MC68HC708AS48 section 16. timer interface (tim) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16.4.2 input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 16.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . .218 16.4.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .219 16.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . .220 16.4.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . .221 16.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .222 16.4.4.3 pwm initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 16.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 16.7 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .226 16.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16.8.1 tim clock pin (ptd6/atd14/tclk) . . . . . . . . . . . . . . . . .22 7 16.8.2 tim channel i/o pins (ptf3/tch5Cptf0/tch2, pte3/tch1Cpte2/tch0) . . . . . . . . . . . . . . . . . . . . . .227 16.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 16.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . .228 16.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . .231 16.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . .232 16.9.4 tim channel status and control registers. . . . . . . . . . . .233 16.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . .238
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 212 timer interface (tim) motorola 16.2 introduction this section describes the timer interface module (tim6). the tim is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 16-1 is a block diagram of the tim. 16.3 features features of the tim include: ? six input capture/output compare channels C rising-edge, falling-edge, or any-edge input capture trigger C set, clear, or toggle output compare action ? buffered and unbuffered pulse width modulation (pwm) signal generation ? programmable tim clock input C 7-frequency internal bus clock prescaler selection C external tim clock input (4-mhz maximum frequency) ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? tim counter stop and reset bits
timer interface (tim) features MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 213 non-disclosure agreement required figure 16-1. tim block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte2 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptd6/atd14/tclk pte2/tch0 pte3/tch1 ptf0/tch2 ptf1/tch3 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte3 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic 16-bit comparator 16-bit latch tch2h:tch2l ms2a els2b els2a ptf0 channel 2 tov2 ch2ie ch2f ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch tch3h:tch3l ms3a els3b els3a ptf1 channel 3 tov3 ch3ie ch3f ch3max logic inter- rupt logic 16-bit comparator 16-bit latch tch4h:tch4l ms4a els4b els4a ptf2 channel 4 tov4 ch4ie ch4f ch5max ms4b logic inter- rupt logic 16-bit comparator 16-bit latch tch5h:tch5l ms5a els5b els5a ptf3 channel 5 tov5 ch5ie ch5f ch5max logic inter- rupt logic ptf2/tch4 ptf3/tch5
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 214 timer interface (tim) motorola addr. register name bit 7 6 5 4 3 2 1 bit 0 $0020 tim status and control register (tsc) see page 229. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0022 tim counter register high (tcnth) see page 231. read: bit 15 14 13 12 11 10 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0023 tim counter register low (tcntl) see page 231. read: bit 7 6 5 4 3 2 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0024 tim modulo register high (tmodh) see page 232. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0025 tim modulo register low (tmodl) see page 232. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0026 tim channel 0 status and control register (tsc0) see page 233. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0027 tim channel 0 register high (tch0h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 tim channel 0 register low (tch0l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0029 tim channel 1 status and control register (tsc1) see page 233. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $002a tim channel 1 register high (tch1h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b tim channel 1 register low (tch1l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002c tim channel 2 status and control register (tsc2) see page 233. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 r = reserved figure 16-2. tim i/o register summary
timer interface (tim) features MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 215 non-disclosure agreement required $002d tim channel 2 register high (tch2h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e tim channel 2 register low (tch2l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $002f tim channel 3 status and control register (tsc3) see page 233. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $0030 tim channel 3 register high (tch3h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 tim channel 3 register low (tch3l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0032 tim channel 4 status and control register (tsc4) see page 233. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset: 0 0 0 0 0 0 0 0 $0033 tim channel 4 register high (tch4h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 tim channel 4 register low (tch4l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0035 tim channel 5 status and control register (tsc5) see page 233. read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset: 0 0 0 0 0 0 0 0 $0036 tim channel 5 register high (tch5h) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 tim channel 5 register low (tch5l) see page 239. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved figure 16-2. tim i/o register summary (continued)
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 216 timer interface (tim) motorola 16.4 functional description figure 16-1 shows the tim structure. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodhCtmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the six tim channels are programmable independently as input capture or output compare channels. 16.4.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, ptd6/atd14/tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 16.4.2 input capture an input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the polarity of the active edge is programmable. the level transition which triggers the counter transfer is defined by the corresponding input edge bits (elsxb and elsxa in tsc0 through tsc5 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. input captures can generate tim cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.
timer interface (tim) functional description MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 217 non-disclosure agreement required the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. the free-running counter contents are transferred to the tim channel status and control register (tsc0Ctsc5, see 16.9.4 tim channel status and control registers ) on each proper signal transition regardless of whether the tim channel flag (ch0fCch5f in tsc0Ctsc5 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or captured is the time of the event. because this value is stored in the input capture register when the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a period, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establish a time reference. in this case, an input capture function is used in conjunction with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 16.9.5 tim channel registers ). because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture register.
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 218 timer interface (tim) motorola 16.4.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 16.4.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 16.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use these methods to synchronize unbuffered changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
timer interface (tim) functional description MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 219 non-disclosure agreement required 16.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte2/tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the pte2/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch0, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf0/tch2 pin. the tim channel registers of the linked pair alternately control the output. setting the ms2b bit in tim channel 2 status and control register (tsc2) links channel 2 and channel 3. the output compare value in the tim channel 2 registers initially controls the output on the ptf0/tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (2 or 3) that control the output are the ones written to last. tsc2 controls and monitors the buffered output compare function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tch3, is available as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the ptf2/tch4 pin. the tim channel registers of the linked pair alternately control the output. setting the ms4b bit in tim channel 4 status and control register (tsc4) links channel 4 and channel 5. the output compare value in the tim channel 4 registers initially controls the output on the ptf2/tch4 pin. writing to the tim channel 5 registers enables the tim channel 5
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 220 timer interface (tim) motorola registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (4 or 5) that control the output are the ones written to last. tsc4 controls and monitors the buffered output compare function, and tim channel 5 status and control register (tsc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3/tch5, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 16.4.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 16-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. figure 16-3. pwm period and pulse width ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface (tim) functional description MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 221 non-disclosure agreement required the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 16.9.1 tim status and control register ). the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 16.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 16.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use these methods to synchronize unbuffered changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ? when changing to a longer pulse width, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 222 timer interface (tim) motorola the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 16.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2/tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the pte2/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tch2 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tim channel 2 status and control register (tsc2) links channel 2 and channel 3. the tim channel 2 registers initially control the pulse width on the ptf0/tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (2 or 3) that control the pulse width are the ones written to last. tsc2 controls and monitors the buffered pwm function, and tim channel 3 status and
timer interface (tim) functional description MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 223 non-disclosure agreement required control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tch3, is available as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered pwm channel whose output appears on the ptf2/tch4 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms4b bit in tim channel 4 status and control register (tsc4) links channel 4 and channel 5. the tim channel 4 registers initially control the pulse width on the ptf2/tch4 pin. writing to the tim channel 5 registers enables the tim channel 5 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (4 or 5) that control the pulse width are the ones written to last. tsc4 controls and monitors the buffered pwm function, and tim channel 5 status and control register (tsc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3/tch5, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. 16.4.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width.
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 224 timer interface (tim) motorola 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxbCmsxa. (see table 16-2 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxbCelsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 16-2 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0hCtch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tim channel 2 registers (tch2hCtch2l) initially control the pwm output. tim status control register 2 (tscr2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. setting ms4b links channels 4 and 5 and configures them for buffered pwm operation. the tim channel 4 registers (tch4hCtch4l) initially control the pwm output. tim status control register 4 (tscr4) controls and monitors the pwm signal from the linked channels. ms4b takes priority over ms4a.
timer interface (tim) interrupts MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 225 non-disclosure agreement required clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. (see 16.9.4 tim channel status and control registers .) 16.5 interrupts these tim sources can generate interrupt requests: ? tim overflow flag (tof) the tof bit is set when the tim counter value rolls over to $0000 after matching the value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. ? tim channel flags (ch5fCch0f) the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. 16.6 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 16.6.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction.
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 226 timer interface (tim) motorola 16.6.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode. 16.7 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit.
timer interface (tim) i/o signals MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 227 non-disclosure agreement required 16.8 i/o signals port d shares one of its pins with the tim. port e shares two of its pins with the tim and port f shares four of its pins with the tim. ptd6/atd14/tclk is an external clock input to the tim prescaler. the six tim channel i/o pins are pte2/tch0, pte3/tch1, ptf0/tch2, ptf1/tch3, ptf2/tch4, and ptf3/tch5. 16.8.1 tim clock pin (ptd6/atd14/tclk) ptd6/atd14/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the ptd6/atd14/tclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. (see 16.9.1 tim status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency ? 2. ptd6/atd14/tclk is available as a general-purpose i/o pin or adc channel when not used as the tim clock input. when the ptd6/atd14/tclk pin is the tim clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 16.8.2 tim channel i/o pins (ptf3/tch5Cptf0/tch2, pte3/tch1Cpte2/tch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. pte2/tch0, pte6/tch2, and ptf2/tch4 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------------------------- t su +
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 228 timer interface (tim) motorola 16.9 i/o registers these i/o registers control and monitor tim operation: ? tim status and control register, tsc ? tim control registers, tcnthCtcntl ? tim counter modulo registers, tmodhCtmodl ? tim channel status and control registers, tsc0, tsc1, tsc2, tsc3, tsc4, and tsc5 ? tim channel registers, tch0hCtch0l, tch1hCtch1l, tch2hCtch2l, tch3hCtch3l, tch4hCtch4l, and tch5hCtch5l 16.9.1 tim status and control register the tim status and control register: ? enables tim overflow interrupts ? flags tim overflows ? stops the tim counter ? resets the tim counter ? prescales the tim counter clock
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 229 non-disclosure agreement required tof tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value. 0 = tim counter has not reached modulo value. toie tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. address: $0020 bit 7 654321 bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 00100000 r = reserved figure 16-4. tim status and control register (tsc)
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 230 timer interface (tim) motorola trst tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] prescaler select bits these read/write bits select either the ptd6/atd14/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 16-1 shows. reset clears the ps[2:0] bits. table 16-1. prescaler selection ps[2:0] tim clock source 000 internal bus clock ? 1 001 internal bus clock ? 2 010 internal bus clock ? 4 011 internal bus clock ? 8 100 internal bus clock ? 16 101 internal bus clock ? 32 110 internal bus clock ? 64 111 ptd6/atd14/tclk
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 231 non-disclosure agreement required 16.9.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if tcnth is read during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. register name and address: tcnth $0022 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: rrrrrrrr reset: 00000000 register name and address: tcntl $0023 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: rrrrrrrr reset: 00000000 r = reserved figure 16-5. tim counter registers (tcnth and tcntl)
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 232 timer interface (tim) motorola 16.9.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. register name and address: tmodh $0024 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11111111 register name and address: tmodl $0025 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11111111 r r = reserved figure 16-6. tim counter modulo registers (tmodh and tmodl)
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 233 non-disclosure agreement required 16.9.4 tim channel status and control registers each of the tim channel status and control registers: ? flags input captures and output compares ? enables input capture and output compare interrupts ? selects input capture, output compare, or pwm operation ? selects high, low, or toggling output on output compare ? selects rising edge, falling edge, or any edge as the active input capture trigger ? selects output toggling on tim overflow ? selects 100% pwm duty cycle ? selects buffered or unbuffered output compare/pwm operation register name and address: tsc0 $0026 bit 7 654321 bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 register name and address: tsc1 $0029 bit 7 654321 bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 00000000 figure 16-7. tim channel status and control registers (tsc0Ctsc5)
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 234 timer interface (tim) motorola register name and address: tsc2 $002c bit 7 654321 bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 register name and address: tsc3 $002f bit 7 654321 bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 00000000 register name and address: tsc4 $0032 bit 7 654321 bit 0 read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset: 00000000 register name and address: tsc5 $0035 bit 7 654321 bit 0 read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset: 00000000 r = reserved figure 16-7. tim channel status and control registers (tsc0Ctsc5) (continued)
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 235 non-disclosure agreement required chxf channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when chxie = 0, clear chxf by reading tim channel x status and control register with chxf set, and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie channel x interrupt enable bit this read/write bit enables tim cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0, tim channel 2, and tim channel 4 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3 to general-purpose i/o. setting ms4b disables the channel 5 status and control register and reverts tch5 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 236 timer interface (tim) motorola msxa mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. (see table 16-2 .) 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. (see table 16-2 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e or port f, and pin ptex/tchx or pin ptfx/tchx is available as a general-purpose i/o pin. table 16-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits.
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 237 non-disclosure agreement required note: before enabling a tim channel register for input capture operation, make sure that the ptex/tchx pin or ptfx/tchx pin is stable for at least two bus clocks. tovx toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. table 16-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 238 timer interface (tim) motorola chxmax channel x maximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 16-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 16-8. chxmax latency 16.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 1 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 239 non-disclosure agreement required register name and address: tch0h $0027 bit 7 654321 bit 0 read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset: indeterminate after reset register name and address: tch0l $0028 bit 7 654321 bit 0 read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write reset: indeterminate after reset register name and address: tch1h $002a bit 7 654321 bit 0 read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset: indeterminate after reset register name and address: tch1l $002b bit 7 654321 bit 0 read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write reset: indeterminate after reset register name and address: tch2h $002d bit 7 654321 bit 0 read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset: indeterminate after reset figure 16-9. tim channel registers (tch0h/lCtch3h/l) (sheet 1 of 3)
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 240 timer interface (tim) motorola register name and address: tch2l $002e bit 7 654321 bit 0 read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write reset: indeterminate after reset register name and address: tch3h $0030 bit 7 654321 bit 0 read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset: indeterminate after reset register name and address: tch3l $0031 bit 7 654321 bit 0 read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write reset: indeterminate after reset register name and address: tch4h $0033 bit 7 654321 bit 0 read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset: indeterminate after reset register name and address: tch4l $0034 bit 7 654321 bit 0 read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write reset: indeterminate after reset figure 16-9. tim channel registers (tch0h/lCtch3h/l) (sheet 2 of 3)
timer interface (tim) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola timer interface (tim) 241 non-disclosure agreement required register name and address: tch5h $0036 bit 7 654321 bit 0 read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset: indeterminate after reset register name and address: tch5l $0037 bit 7 654321 bit 0 read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write reset: indeterminate after reset figure 16-9. tim channel registers (tch0h/lCtch3h/l) (sheet 3 of 3)
non-disclosure agreement required timer interface (tim) advance information MC68HC708AS48 rev. 4.0 242 timer interface (tim) motorola
MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 243 non-disclosure agreement required advance information MC68HC708AS48 section 17. serial communications interface (sci) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 17.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.4.3 character length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.4.4 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . .249 17.4.5 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 17.4.6 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 17.4.7 inversion of transmitted output . . . . . . . . . . . . . . . . . . . .253 17.4.8 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 17.4.9 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 17.4.10 character length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 17.4.11 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 17.4.12 data sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 17.4.13 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 17.4.14 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 17.5 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 17.5.1 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 17.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .263 17.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 17.8.1 pte0/txd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . .264 17.8.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . .264
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 244 serial communications interface (sci) motorola 17.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 17.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .265 17.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .271 17.9.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 17.9.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 17.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 17.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . .280 17.2 introduction this section describes the serial communications interface module (sci, version d), which allows high-speed asynchronous communications with peripheral devices and other mcus. 17.3 features features of the sci module include: ? full duplex operation ? standard mark/space non-return-to-zero (nrz) format ? 32 programmable baud rates ? programmable 8-bit or 9-bit character length ? separately enabled transmitter and receiver ? separate receiver and transmitter cpu interrupt requests ? programmable transmitter output polarity ? two receiver wakeup methods: C idle line wakeup C address mark wakeup
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 245 non-disclosure agreement required ? interrupt-driven operation with eight interrupt flags: C transmitter empty C transmission complete C receiver full C idle receiver input C receiver overrun C noise error C framing error C parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection 17.4 functional description figure 17-1 shows the structure of the sci module. the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data.
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 246 serial communications interface (sci) motorola figure 17-1. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci pte1/rxd pte0/txd internal bus txinv loops ? 4 ? 16 pre- scaler baud rate generator cgmxclk
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 247 non-disclosure agreement required addr. register name bit 7 6 5 4 3 2 1 bit 0 $0013 sci control register 1 (scc1) see page 266. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 269. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 272. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 274. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 278. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 279. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 280. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 r = reserved u = unaffected figure 17-2. sci i/o register summary
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 248 serial communications interface (sci) motorola 17.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 17-3 . figure 17-3. sci data formats 17.4.2 transmitter figure 17-4 shows the structure of the sci transmitter. 17.4.3 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scc1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scc1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 249 non-disclosure agreement required 17.4.4 character transmission during an sci transmission, the transmit shift register shifts a character out to the pte0/txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. initialize the tx and rx rate in the sci baud register (scbr) ($0019) 17.9.7 sci baud rate register . 2. enable the sci by writing a logic 1 to ensci in sci control register 1 (scc1) ($0013). 3. enable the transmitter by writing a logic 1 to the transmitter enable bit (te) in sci control register 2 (scc2) ($0014). 4. clear the sci transmitter empty bit (scte) by first reading sci status register (scs1) ($0016) and then writing to the scdr ($0018). 5. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of 10 or 11 logic 1s. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte in the sci status control register (scs1), becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, scti e (scc2), is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte0/txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins.
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 250 serial communications interface (sci) motorola figure 17-4. sci transmitter pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc cgmxclk parity generation msb sci data register load from scdr shift enable preamble all ones break all zeros transmitter control logic shift register tc sctie tcie scte transmitter cpu interrupt request m ensci loops te pte0/txd txinv internal bus ? 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider ? 16
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 251 non-disclosure agreement required addr. register name bit 7 6 5 4 3 2 1 bit 0 $0013 sci control register 1 (scc1) see page 266. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 269. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 272. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 274. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 278. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 279. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 280. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 r = reserved u = unaffected figure 17-5. transmitter i/o register summary
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 252 serial communications interface (sci) motorola 17.4.5 break characters writing a logic 1 to the send break bit, sbk (scc2), loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit (scc1). as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: ? sets the framing error bit (fe) in scs1 ? sets the sci receiver full bit (scrf) in scs1 ? clears the sci data register (scdr) ? clears the r8 bit in scc3 ? sets the break flag bit (bkf) in scs2 ? may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 253 non-disclosure agreement required 17.4.6 idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit (mode character length) in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit (transmitter enable) is cleared during a transmission, the pte0/txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the pte0/txd pin. setting te after the stop bit appears on pte0/txd causes data previously written to the scdr to be lost. a good time to toggle the te bit is when the scte bit becomes set and just before writing the next byte to the scdr. 17.4.7 inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 17.9.1 sci control register 1 .)
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 254 serial communications interface (sci) motorola 17.4.8 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: ? sci transmitter empty (scte) the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie (scc2), enables the scte bit to generate transmitter cpu interrupt requests. ? transmission complete (tc) the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie (scc2), enables the tc bit to generate transmitter cpu interrupt requests. 17.4.9 receiver figure 17-6 shows the structure of the sci receiver.
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 255 non-disclosure agreement required figure 17-6. sci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe pte1/rxd internal bus pre- scaler baud divider ? 4 ? 16 scp1 scp0 scr2 scr1 scr0 cgmxclk
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 256 serial communications interface (sci) motorola addr. register name bit 7 6 5 4 3 2 1 bit 0 $0013 sci control register 1 (scc1) see page 266. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) see page 269. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) see page 272. read: r8 t8 r r orie neie feie peie write: r reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) see page 274. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) see page 278. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) see page 279. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 280. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: r r reset: 0 0 0 0 0 0 0 0 r = reserved u = unaffected figure 17-7. sci receiver i/o register summary
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 257 non-disclosure agreement required 17.4.10 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 17.4.11 character reception during an sci reception, the receive shift register shifts characters in from the pte1/rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie (scc2), is also set, the scrf bit generates a receiver cpu interrupt request.
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 258 serial communications interface (sci) motorola 17.4.12 data sampling the receiver samples the pte1/rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 17-8 ): ? after every start bit ? after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 17-8. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 259 non-disclosure agreement required to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 17-1 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 17-2 summarizes the results of the data bit samples. table 17-1. start bit veri?cation rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 17-2. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 260 serial communications interface (sci) motorola note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 17-3 summarizes the results of the stop bit samples. 17.4.13 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit (scs1) is set. a break character that has no stop bit also sets the fe bit. 17.4.14 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu (scc2), puts the receiver into a standby state during which receiver interrupts are disabled. table 17-3. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
serial communications interface (sci) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 261 non-disclosure agreement required depending on the state of the wake bit in scc1, either of two conditions on the pte1/rxd pin can bring the receiver out of the standby state: ? address mark an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. ? idle input line condition when the wake bit is clear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: clearing the wake bit after the pte1/rxd pin has been idle may cause the receiver to wake up immediately.
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 262 serial communications interface (sci) motorola 17.5 receiver interrupts these sources can generate cpu interrupt requests from the sci receiver: ? sci receiver full (scrf) the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie (scc2), enables the scrf bit to generate receiver cpu interrupts. ? idle input (idle) the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the pte1/rxd pin. the idle line interrupt enable bit, ilie (scc2), enables the idle bit to generate cpu interrupt requests. 17.5.1 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: ? receiver overrun (or) the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie (scc3), enables or to generate sci error cpu interrupt requests. ? noise flag (nf) the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie (scc3), enables nf to generate sci error cpu interrupt requests. ? framing error (fe) the fe bit in scs1 is set when a logic zero occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie (scc3), enables fe to generate sci error cpu interrupt requests. ? parity error (pe) the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie (scc3), enables pe to generate sci error cpu interrupt requests.
serial communications interface (sci) low-power modes MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 263 non-disclosure agreement required 17.6 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 17.6.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 17.6.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. 17.7 sci during break module interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic z0ero to the bcfe bit. with bcfe at logic 0 (its default state), software can read and
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 264 serial communications interface (sci) motorola write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 17.8 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: ? pte0/txd transmit data ? pte1/rxd receive data 17.8.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from the sci transmitter. the sci shares the pte0/txd pin with port e. when the sci is enabled, the pte0/txd pin is an output regardless of the state of the ddre0 bit in data direction register e (ddre). 17.8.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when the sci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre).
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 265 non-disclosure agreement required 17.9 i/o registers these i/o registers control and monitor sci operation: ? sci control register 1, scc1 ? sci control register 2, scc2 ? sci control register 3, scc3 ? sci status register 1, scs1 ? sci status register 2, scs2 ? sci data register, scdr ? sci baud rate register, scbr 17.9.1 sci control register 1 sci control register 1: ? enables loop mode operation ? enables the sci ? controls output polarity ? controls character length ? controls sci wakeup method ? controls idle character detection ? enables parity function ? controls parity type
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 266 serial communications interface (sci) motorola loops loop mode select bit this read/write bit enables loop mode operation. in loop mode the pte1/rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, including idle, break, start, and stop bits. address: $0013 bit 7 654321 bit 0 read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 figure 17-9. sci control register 1 (scc1)
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 267 non-disclosure agreement required m mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. (see table 17-4 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the pte1/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty idle line type bit this read/write bit determines when the sci starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit can cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen parity enable bit this read/write bit enables the sci parity function. (see table 17-4 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 17-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 268 serial communications interface (sci) motorola pty parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. (see table 17-4 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. table 17-4. character format selection control bits character format m pen:pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 269 non-disclosure agreement required 17.9.2 sci control register 2 sci control register 2: ? enables these cpu interrupt requests: C enables the scte bit to generate transmitter cpu interrupt requests C enables the tc bit to generate transmitter cpu interrupt requests C enables the scrf bit to generate receiver cpu interrupt requests C enables the idle bit to generate receiver cpu interrupt requests ? enables the transmitter ? enables the receiver ? enables sci wakeup ? transmits sci break characters sctie sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt requests 0 = scte not enabled to generate cpu interrupt requests tcie transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests address: $0014 bit 7 654321 bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 figure 17-10. sci control register 2 (scc2)
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 270 serial communications interface (sci) motorola scrie sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt requests 0 = scrf not enabled to generate cpu interrupt requests ilie idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pte0/txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the pte0/txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1.
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 271 non-disclosure agreement required rwu receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk send break bit setting and then clearing this read/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters transmitted note: do not toggle the sbk bit immediately after setting the scte bit because toggling sbk too early causes the sci to send a break character instead of a preamble. 17.9.3 sci control register 3 sci control register 3: ? stores the ninth sci data bit received and the ninth sci data bit to be transmitted ? enables these interrupts: C receiver overrun interrupts C noise error interrupts C framing error interrupts C parity error interrupts
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 272 serial communications interface (sci) motorola r8 received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other eight bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. orie receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt requests from or bit disabled neie receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled address: $0015 bit 7 654321 bit 0 read: r8 t8 r r orie neie feie peie write: r reset: u u 000000 r = reserved u = unaffected figure 17-11. sci control register 3 (scc3)
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 273 non-disclosure agreement required feie receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see figure 17-12 .) reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled 17.9.4 sci status register 1 sci status register 1 contains flags to signal these conditions: ? transfer of scdr data to transmit shift register complete ? transmission complete ? transfer of receive shift register data to scdr complete ? receiver input idle ? receiver overrun ? noisy data ? framing error ? parity error
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 274 serial communications interface (sci) motorola scte sci transmitter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register note: setting the te bit for the first time also sets the scte bit. setting the te and sctie bits generates an sci transmitter cpu request. tc transmission complete bit this read-only bit is set when the scte bit is set and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break character is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break character and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress address: $0016 bit 7 654321 bit 0 read: scte tc scrf idle or nf fe pe write: rrrrrrrr reset: 11000000 r = reserved figure 17-12. sci status register 1 (scs1)
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 275 non-disclosure agreement required scrf sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set and the dmare bit in scc3 is clear. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) or receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 17-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2.
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 276 serial communications interface (sci) motorola in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the pte1/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 277 non-disclosure agreement required figure 17-13. flag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 278 serial communications interface (sci) motorola 17.9.5 sci status register 2 sci status register 2 contains flags to signal two conditions: 1. break character detected 2. incoming data bkf break flag bit this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the pte1/rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits, usually from noise or a baud rate mismatch or when the receiver detects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7 654321 bit 0 read: rrrrrr bkf rpf write: r r reset: 00000000 r = reserved figure 17-14. sci status register 2 (scs2)
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 279 non-disclosure agreement required 17.9.6 sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7:r0/t0 receive/transmit data bits reading address $0018 accesses the read-only received data bits, r7:r0. writing to address $0018 writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. address: $0018 bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 17-15. sci data register (scdr)
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 280 serial communications interface (sci) motorola 17.9.7 sci baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 17-5 . reset clears scp1 and scp0. scr2:scr0 sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 17-6 . reset clears scr2:scr0. address: $0019 bit 7 654321 bit 0 read: r r scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 r = reserved figure 17-16. sci baud rate register 1 (scbr) table 17-5. sci baud rate prescaling scp1:scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13
serial communications interface (sci) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial communications interface (sci) 281 non-disclosure agreement required use this formula to calculate the sci baud rate: pd = prescale divisor (see table 17-5 ) bd = baud rate divisor (see table 17-6 ) table 17-6. sci baud rate selection scr2:scr1:scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate cgmxclk 64 pd bd ------------------------------------ =
non-disclosure agreement required serial communications interface (sci) advance information MC68HC708AS48 rev. 4.0 282 serial communications interface (sci) motorola table 17-7 shows the sci baud rates that can be generated with a 4.194-mhz crystal. table 17-7. sci baud rate selection examples scp1:scp0 prescaler divisor (pd) scr2:scr1:scr0 baud rate divisor (bd) baud rate (f xclk = 4.194 mhz) 00 1 000 1 65,531 00 1 001 2 32,766 00 1 010 4 16,383 00 1 011 8 8191 00 1 100 16 4095 00 1 101 32 2048 00 1 110 64 1024 00 1 111 128 512 01 3 000 1 21,844 01 3 001 2 10,922 01 3 010 4 5461 01 3 011 8 2730 01 3 100 16 1365 01 3 101 32 683 01 3 110 64 341 01 3 111 128 171 10 4 000 1 16,383 10 4 001 2 8191 10 4 010 4 4096 10 4 011 8 2048 10 4 100 16 1024 10 4 101 32 512 10 4 110 64 256 10 4 111 128 128 11 13 000 1 5041 11 13 001 2 1664 11 13 010 4 1260 11 13 011 8 630 11 13 100 16 315 11 13 101 32 158 11 13 110 64 78.8 11 13 111 128 39.4
MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 283 non-disclosure agreement required advance information MC68HC708AS48 section 18. serial peripheral interface (spi) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 18.4 pin name and register name conventions . . . . . . . . . . . . . .285 18.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 18.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 18.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 18.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 18.6.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . .290 18.6.2 transmission format when cpha = 0 . . . . . . . . . . . . . . .291 18.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . .292 18.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . .294 18.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 18.7.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 18.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 18.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.9 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . .301 18.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 18.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .305 18.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 18.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . .306 18.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . .307
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 284 serial peripheral interface (spi) motorola 18.13.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 18.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 18.13.5 v ss (clock ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 18.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 18.14.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 18.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . .312 18.14.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 18.2 introduction this section describes the serial peripheral interface (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 18.3 features features of the spi module include: ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? four master mode frequencies (maximum = bus frequency ? 2) ? maximum slave mode frequency = bus frequency ? serial clock with programmable polarity and phase ? two separately enabled interrupts with cpu service: C sprf, spi receiver full C spte, spi transmitter empty ? mode fault error flag with cpu interrupt capability ? overflow error flag with cpu interrupt capability ? programmable wired-or mode ?i 2 c (inter-integrated circuit) compatibility
serial peripheral interface (spi) pin name and register name conventions MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 285 non-disclosure agreement required 18.4 pin name and register name conventions the generic names of the spi input/output (i/o) pins are: ? ss (slave select) ? spsck (spi serial clock) ? mosi (master out slave in) ? miso (master in slave out) the spi shares four i/o pins with a parallel i/o port. the full name of an spi pin reflects the name of the shared port pin. table 18-1 shows the full names of the spi i/o pins. the generic pin names appear in the text that follows. the generic names of the spi i/o registers are: ? spi control register (spcr) ? spi status and control register (spscr) ? spi data register (spdr) table 18-2 shows the names and the addresses of the spi i/o registers. table 18-1. pin name conventions spi generic pin name: miso mosi ss spsck full spi pin name: pte5/miso pte6/mosi pte4/ ss pte7/spsck table 18-2. i/o register addresses register name address spi control register (spcr) $0010 spi status and control register (spscr) $0011 spi data register (spdr) $0012
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 286 serial peripheral interface (spi) motorola 18.5 functional description figure 18-1 summarizes the spi i/o registers and figure 18-2 shows the structure of the spi module. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0010 spi control register (spcr) see page 310. read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $0011 spi status and control register (spscr) see page 313. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 $0012 spi data register (spdr) see page 316. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset r = reserved figure 18-1. spi i/o register summary
serial peripheral interface (spi) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 287 non-disclosure agreement required figure 18-2. spi module block diagram the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. all spi interrupts can be serviced by the cpu. the operation of the spi module is described here. transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 clock select ? 2 clock divider ? 8 ? 32 ? 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus bus clock modfen errie control modf spmstr mosi miso spsck ss
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 288 serial peripheral interface (spi) motorola 18.5.1 master mode the spi operates in master mode when the spi master bit, spmstr (spcr $0010), is set. note: configure the spi modules as master and slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. (see 18.14.1 spi control register .) only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte (spscr $0011). the byte begins shifting out on the mosi pin under the control of the serial clock. (see figure 18-3 .) the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 18.14.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. figure 18-3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
serial peripheral interface (spi) functional description MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 289 non-disclosure agreement required as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the masters miso pin. the transmission ends when the receiver full bit, sprf (spscr), becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register and then reading the spi data register. writing to the spi data register clears the sptie bit. 18.5.2 slave mode the spi operates in slave mode when the spmstr bit (spcr $0010) is clear. in slave mode the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave mcu must be at logic 0. ss must remain low until the transmission is complete. (see 18.7.2 mode fault error .) in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it is transferred to the receive data register, and the sprf bit (spscr) is set. to prevent an overflow condition, slave software then must read the spi data register before another byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed, which is twice as fast as the fastest master spsck clock that can be generated. the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. otherwise the byte already in the slave shift register shifts out on the miso pin.
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 290 serial peripheral interface (spi) motorola data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 18.6 transmission formats .) if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. note: to prevent spsck from appearing as a clock edge, spsck must be in the proper idle state before the slave is enabled. 18.6 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line synchronizes shifting and sampling on the two serial data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can be used optionally to indicate a multiple-master bus contention. 18.6.1 clock phase and polarity controls software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. the clock phase (cpha) control bit (spcr) selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note: before writing to the cpol bit or the cpha bit (spcr), disable the spi by clearing the spi enable bit (spe).
serial peripheral interface (spi) transmission formats MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 291 non-disclosure agreement required 18.6.2 transmission format when cpha = 0 figure 18-4 shows an spi transmission in which cpha (spcr) is logic 0. the figure should not be used as a replacement for data sheet parametric information.two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input ( ss) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 18.7.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low again between each byte transmitted as shown in figure 18-5 . figure 18-4. transmission format (cpha = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol = 1 mosi from master miso from slave ss to slave capture strobe
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 292 serial peripheral interface (spi) motorola figure 18-5. cpha/ ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss. any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. 18.6.3 transmission format when cpha = 1 figure 18-6 shows an spi transmission in which cpha (spcr) is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input ( ss) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 18.7.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
serial peripheral interface (spi) transmission formats MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 293 non-disclosure agreement required preferable in systems having only one master and only one slave driving the miso data line. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. figure 18-6. transmission format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol =1 mosi from master miso from slave ss to slave capture strobe
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 294 serial peripheral interface (spi) motorola 18.6.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), transmissions are started by a software write to the spdr ($0012). cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sck signal. when cpha = 0, the sck signal remains inactive for the first half of the first sck cycle. when cpha = 1, the first sck cycle begins with an edge on the sck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 18-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. it is only enabled when both the spe and spmstr bits (spcr) are set to conserve power. sck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr will occur relative to the slower sck. this uncertainty causes the variation in the initiation delay shown in figure 18-7 . this delay will be no longer than a single spi bit time. that is, the maximum delay between the write to spdr and the start of the spi transmission is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128.
serial peripheral interface (spi) transmission formats MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 295 non-disclosure agreement required figure 18-7. transmission start delay (master) write to spdr initiation delay bus mosi sck cpha = 1 sck cpha = 0 sck cycle number msb bit 6 12 clock write to spdr earliest latest sck = internal clock ? 2; earliest latest 2 possible start points sck = internal clock ? 8; 8 possible start points earliest latest sck = internal clock ? 32; 32 possible start points earliest latest sck = internal clock ? 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? initiation delay from write spdr to transfer begin
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 296 serial peripheral interface (spi) motorola 18.7 error conditions two flags signal spi error conditions: 1. overflow (ovrfin spscr) failing to read the spi data register before the next byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the spi data register. ovrf is in the spi status and control register. 2. mode fault error (modf in spscr) the modf bit indicates that the voltage on the slave select pin ( ss) is inconsistent with the mode of the spi. modf is in the spi status and control register. 18.7.1 overflow error the overflow flag (ovrf in spscr) becomes set if the spi receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. (see figure 18-4 and figure 18-6 .) if an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. therefore, an overflow error always indicates the loss of data. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 18-10 .) it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if an end-of-block transmission interrupt was meant to pull the mcu out of wait, having an overflow condition without overflow interrupts enabled causes the mcu to hang in wait mode. if the ovrf is enabled to generate an interrupt, it can pull the mcu out of wait mode instead. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 18-8 shows how it is possible to miss an overflow.
serial peripheral interface (spi) error conditions MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 297 non-disclosure agreement required figure 18-8. missed read of overflow condition the first part of figure 18-8 shows how to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf flag can be set in between the time that spscr and spdr are read. in this case, an overflow can be easily missed. since no more sprf interrupts can be generated until this ovrf is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr after the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions will complete with an sprf interrupt. figure 18-9 illustrates this process. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit (spscr). read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscrw with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is set. byte 4 is lost. and ovrf bit clear. and ovrf bit clear.
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 298 serial peripheral interface (spi) motorola figure 18-9. clearing sprf when ovrf interrupt is not enabled 18.7.2 mode fault error for the modf flag (in spscr) to be set, the mode fault error enable bit (modfen in spscr) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 18-10 .) it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear.
serial peripheral interface (spi) error conditions MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 299 non-disclosure agreement required in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes these events to occur: ? if errie = 1, the spi generates an spi receiver/error cpu interrupt request. ? the spe bit is cleared. ? the spte bit is set. ? the spi state counter is cleared. ? the data direction register of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all data direction register (ddr) bits associated with the spi shared port pins. note: setting the modf flag (spscr) does not clear the spmstr bit. reading spmstr when modf = 1 will indicate a mode fault error occurred in either master mode or slave mode. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck returns to its idle level after the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level after the shift of the last data bit. (see 18.6 transmission formats .) note: when cpha = 0, a modf occurs if a slave is selected ( ss is at logic 0) and later unselected ( ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 300 serial peripheral interface (spi) motorola bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by toggling the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if a transmission has begun. to clear the modf flag, read the spscr and then write to the spcr register. this entire clearing procedure must occur with no modf condition existing or else the flag will not be cleared. 18.8 interrupts four spi status flags can be enabled to generate cpu interrupt requests: the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests. the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt, provided that the spi is enabled (spe = 1). the error interrupt enable bit (errie) enables both the modf and ovrf flags to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf flag is enabled to generate receiver/error cpu interrupt requests. table 18-3. spi interrupts flag request spte (transmitter empty) spi transmitter cpu interrupt request (sptie = 1) sprf (receiver full) spi receiver cpu interrupt request (sprie = 1) ovrf (over?ow) spi receiver/error interrupt request (sprie = 1, errie = 1) modf (mode fault) spi receiver/error interrupt request (sprie = 1, errie = 1, modfen = 1)
serial peripheral interface (spi) queuing transmission data MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 301 non-disclosure agreement required figure 18-10. spi interrupt request generation two sources in the spi status and control register can generate cpu interrupt requests: 1. spi receiver full bit (sprf) the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate an spi receiver/error cpu interrupt request. 2. spi transmitter empty (spte) the spte bit becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate an spte cpu interrupt request. 18.9 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag (spte in spscr) indicates when the transmit data buffer is ready to accept new data. write to the spi data register only when the spte bit is high. figure 18-11 shows the timing associated with doing back-to-back transmissions with the spi (spsck has cpha: cpol = 1:0). spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 302 serial peripheral interface (spi) motorola figure 18-11. sprf/spte cpu interrupt timing the transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. bit 3 mosi spsck (cpha:cpol = 1:0) spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing byte 1 transfers from transmit data 3 1 2 2 3 5 spte bit. register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set.
serial peripheral interface (spi) resetting the spi MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 303 non-disclosure agreement required 18.10 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, these occurs: ? the spte flag is set. ? any transmission currently in progress is aborted. ? the shift register is cleared. ? the spi state counter is cleared, making it ready for a new complete transmission. ? all the spi port logic is defaulted back to being general-purpose i/o. these additional items are reset only by a system reset: ? all control bits in the spcr register ? all control bits in the spscr register (modfen, errie, spr1, and spr0) ? the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to reset all control bits when spe is set back to high for the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi also can be disabled by a mode fault occurring in an spi that was configured as a master with the modfen bit set.
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 304 serial peripheral interface (spi) motorola 18.11 low-power modes the wait and stop instructions put the mcu in low-power standby modes. 18.11.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode, the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occurs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). (see 18.8 interrupts .) 18.11.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after the mcu exits stop mode. if stop mode is exited by reset, any transfer in progress is aborted and the spi is reset.
serial peripheral interface (spi) spi during break interrupts MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 305 non-disclosure agreement required 18.12 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr $fe03) enables software to clear status bits during the break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the data register in break mode will not initiate a transmission nor will this data be transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect.
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 306 serial peripheral interface (spi) motorola 18.13 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. ? miso data received ? mosi data transmitted ? spsck serial clock ? ss slave select ?v ss clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 18.13.1 miso (master in/slave out) miso is one of the two spi module pins that transmit serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the miso pin regardless of the state of the data direction register of the shared i/o port.
serial peripheral interface (spi) i/o signals MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 307 non-disclosure agreement required 18.13.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmit serial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mosi pin regardless of the state of the data direction register of the shared i/o port. 18.13.3 spsck (serial clock) the serial clock synchronizes data transmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port.
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 308 serial peripheral interface (spi) motorola 18.13.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 18.6 transmission formats .) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low throughout the transmission for the cpha = 1 format. see figure 18-12 . figure 18-12. cpha/ ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 18.14.2 spi status and control register .) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if a transmission already has begun. when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. (see 18.7.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
serial peripheral interface (spi) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 309 non-disclosure agreement required the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the data register. (see table 18-4 .) 18.13.5 v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize radio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin. 18.14 i/o registers three registers control and monitor spi operation: ? spi control register (spcr, $0010) ? spi status and control register (spscr, $0011) ? spi data register (spdr, $0012) table 18-4. spi con?guration spe spmstr modfen spi configuration state of ss logic 0 x x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi x = dont care
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 310 serial peripheral interface (spi) motorola 18.14.1 spi control register the spi control register: ? enables spi module interrupt requests ? selects cpu interrupt requests ? configures the spi module as master or slave ? selects serial clock polarity and phase ? configures the spsck, mosi, and miso pins as open-drain outputs ? enables the spi module sprie spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode address: $0010 bit 7 654321 bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 00101000 r = reserved figure 18-13. spi control register (spcr)
serial peripheral interface (spi) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 311 non-disclosure agreement required cpol clock polarity bit this read/write bit determines the logic state of the spsck pin between transmissions. (see figure 18-4 and figure 18-6 .) to transmit data between spi modules, the spi modules must have identical cpol bits. reset clears the cpol bit. cpha clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 18-4 and figure 18-6 .) to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 18-12 .) reset sets the cpha bit. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss. any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set. (see 18.7.2 mode fault error .) a logic 1 on the ss pin does not in any way affect the state of the spi state machine. spwom spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsck, mosi, and miso pins
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 312 serial peripheral interface (spi) motorola spe spi enable bit this read/write bit enables the spi module. clearing spe causes a partial reset of the spi. (see 18.10 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie spi transmit interrupt enable bit this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 18.14.2 spi status and control register the spi status and control register contains flags to signal these conditions: ? receive data register full ? failure to clear sprf bit before next byte is received (overflow error) ? inconsistent logic level on ss pin (mode fault error) ? transmit data register empty the spi status and control register also contains bits that perform these functions: ? enable error interrupts ? enable mode fault error detection ? select master spi baud rate
serial peripheral interface (spi) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 313 non-disclosure agreement required sprf spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. any read of the spi data register clears the sprf bit. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie error interrupt enable bit this read-only bit enables the modf and ovrf flags to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the spi data register. reset clears the ovrf flag. 1 = overflow 0 = no overflow address: $0011 bit 7 654321 bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 00001000 r = reserved figure 18-14. spi status and control register (spscr)
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 314 serial peripheral interface (spi) motorola modf mode fault bit this clearable, ready-only flag is set in a slave spi if the ss pin goes high during a transmission. in a master spi, the modf flag is set if the ss pin goes low at any time. clear the modf bit by reading the spi status and control register with modf set and then writing to the spi data register. reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note: do not write to the spi data register unless the spte bit is high. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since the transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not available as a general purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardless of the value of modfen. (see 18.13.4 ss (slave select) .)
serial peripheral interface (spi) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola serial peripheral interface (spi) 315 non-disclosure agreement required if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 18.7.2 mode fault error .) spr1 and spr0 spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 18-5 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm), see section 8. clock generator module (cgm) . bd = baud rate divisor table 18-5. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- bus clock bd ------------------------- ==
non-disclosure agreement required serial peripheral interface (spi) advance information MC68HC708AS48 rev. 4.0 316 serial peripheral interface (spi) motorola 18.14.3 spi data register the spi data register is the read/write buffer for the receive data register and the transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate buffers that can contain different values. see figure 18-2 . r7:r0/t7:t0 receive/transmit data bits note: do not use read-modify-write instructions on the spi data register since the buffer read is not the same as the buffer written. address: $0012 bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 18-15. spi data register (spdr)
MC68HC708AS48 rev. 4.0 advance information motorola analog-to-digital converter (adc) 317 non-disclosure agreement required advance information MC68HC708AS48 section 19. analog-to-digital converter (adc) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 19.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 19.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 19.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 19.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .321 19.4.5 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . .321 19.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 19.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 19.7.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . .322 19.7.2 adc analog ground pin (v ssa )/adc voltage reference low pin (v refl ). . . . . . . . . . . . . . .323 19.7.3 adc voltage in (adcvin). . . . . . . . . . . . . . . . . . . . . . . . .323 19.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 19.8.1 adc status and control register . . . . . . . . . . . . . . . . . . .324 19.8.2 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 19.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . .327
non-disclosure agreement required analog-to-digital converter (adc) advance information MC68HC708AS48 rev. 4.0 318 analog-to-digital converter (adc) motorola 19.2 introduction this section describes the 8-bit analog-to-digital converter (adc). 19.3 features features of the adc module include: ? 15 channels (52-pin plcc), 16 channels (64-pin qfp) with multiplexed input ? linear successive approximation ? 8-bit resolution ? single or continuous conversion ? conversion complete flag or conversion complete interrupt ? selectable adc clock 19.4 functional description fifteen adc channels are available in the 52-plcc (MC68HC708AS48cfn) for sampling external sources at pins ptd6/atd14/tclk C ptd0/atd8 and ptb7/atd7 C ptb0/atd0. sixteen adc channels are available in the 64-qfp (engineering sample) for sampling external sources at pins ptd7/atd15 C ptd0/atd8 and ptb7/atd7 C ptb0/atd0 . an analog multiplexer allows the single adc converter to select one of the adc channels as adc voltage input (adcvin). adcvin is converted by the successive approximation register-based counters. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. (see figure 19-1 .)
analog-to-digital converter (adc) functional description MC68HC708AS48 rev. 4.0 advance information motorola analog-to-digital converter (adc) 319 non-disclosure agreement required figure 19-1. adc block diagram 19.4.1 adc port i/o pins ptd7/atd15 - ptd0/atd8 and ptb7/atd7-ptb0/atd0 are general-purpose i/o pins that are shared with the adc channels. ptd2/atd10 is an input-only pin that is also shared with an adc channel. note: ptd7/atd15 is available only on the 64-pin qfp package. the channel select bits (adc status control register, $0038), define which adc channel/port pin will be used as the input signal. the adc internal data bus read ddrb/ddrb write ddrb/ddrd reset write ptb/ptd read ptb/ptd ptbx/ptdx ddrbx/ddrdx ptbx/ptdx interrupt logic adc clock generator conversion complete adc voltage in adcvin adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x channel select
non-disclosure agreement required analog-to-digital converter (adc) advance information MC68HC708AS48 rev. 4.0 320 analog-to-digital converter (adc) motorola overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. note: do not use adc channel atd14 when using the ptd6/atd14/tclk pin as the clock input for the tim. 19.4.2 voltage conversion when the input voltage to the adc equals v refh (see 21.7 adc characteristics ), the adc converts the signal to $ff (full scale). if the input voltage equals v ssa /v refl, the adc converts it to $00. input voltages between v refh and v ssa /v refl are a straight-line linear conversion. all other input voltages will result in $ff if greater than v refh and $00 if less than v ssa /v refl . note: input voltage should not exceed the analog supply voltages. 19.4.3 conversion time sixteen adc internal clocks are required to perform one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a write to the adscr. if the adc internal clock is selected to run at 1 mhz, then one conversion will take 16 m s to complete. but since the adc can run almost completely asynchronously to the bus clock, (for example, the adc is configured to derive its internal clock from cgmxclk and the bus clock is being derived from the pll within the cgm [cgmout]), this 16 m s conversion can take up to 17 m s to complete. this worst-case could occur if the write to the adscr happened directly after the rising edge of the adc internal clock causing
analog-to-digital converter (adc) interrupts MC68HC708AS48 rev. 4.0 advance information motorola analog-to-digital converter (adc) 321 non-disclosure agreement required the conversion to wait until the next rising edge of the adc internal clock. with a 1 mhz adc internal clock the maximum sample rate is 59 khz to 62 khz. refer to 21.7 adc characteristics . 19.4.4 continuous conversion in the continuous conversion mode the adc continuously converts the selected channel, filling the adc data register with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit (adc status control register, $0038) is set after each conversion and can be cleared by writing the adc status and control register or reading of the adc data register. 19.4.5 accuracy and precision the conversion process is monotonic and has no missing codes. see 21.7 adc characteristics for accuracy information. 19.5 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 16 to 17 adc clock cycles conversion time = ???????????? adc clock frequency number of bus cycles = conversion time x bus frequency
non-disclosure agreement required analog-to-digital converter (adc) advance information MC68HC708AS48 rev. 4.0 322 analog-to-digital converter (adc) motorola 19.6 low-power modes the low-power modes are described here. 19.6.1 wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits in the adc status and control register to logic 1s before executing the wait instruction. 19.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 19.7 i/o signals in the 52-pin plcc package, the adc module has 15 channels that are shared with i/o ports b and d and one channel with an input-only port bit on port d. in the 64-pin qfp package, the adc module has 16 channels that are shared with i/o ports b and d and one channel with an input-only port bit on port d. refer to 21.7 adc characteristics for voltages referenced below. 19.7.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) the adc analog portion uses v dda /v ddaref as its power pin. connect the v dda /v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda /v ddaref for good results. v dda /v ddaref is the high reference voltage for all analog-to-digital conversions. connect the v refh pin to a voltage potential between
analog-to-digital converter (adc) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola analog-to-digital converter (adc) 323 non-disclosure agreement required 1.5 volts and v ddaref /v dda depending on the desired upper conversion boundary. note: route v dda /v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 19.7.2 adc analog ground pin (v ssa )/adc voltage reference low pin (v refl ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same voltage potential as v ss . v refl is the lower reference supply for the adc. connect the v refl pin to a voltage potential between v ssa and 0.5 volts depending on the desired lower conversion boundary. 19.7.3 adc voltage in (adcvin) adcvin is the input voltage signal from one of the adc channels to the adc module. 19.8 i/o registers these i/o registers control and monitor adc operation: ? adc status and control register (adscr) ? adc data register (adr) ? adc clock register (adiclk)
non-disclosure agreement required analog-to-digital converter (adc) advance information MC68HC708AS48 rev. 4.0 324 analog-to-digital converter (adc) motorola 19.8.1 adc status and control register these paragraphs describe the function of the adc status and control register. coco conversions complete bit when the aien bit is a logic 0, the coco is a read-only bit which is set each time a conversion is completed. this bit is cleared whenever the adc status and control register is written or whenever the adc data register is read. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or 0 = cpu interrupt enabled (aien = 1) aien adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $0038 bit 7 654321 bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset: 00011111 r = reserved figure 19-2. adc status and control register (adscr)
analog-to-digital converter (adc) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola analog-to-digital converter (adc) 325 non-disclosure agreement required adco adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5-bit field which is used to select one of the adc channels. the five channel select bits are detailed in table 19-1 . note: care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. the adc subsystem is turned off when the channel select bits are all set to one. this feature allows for reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a logic 1. note: recovery from the disabled state requires one conversion cycle to stabilize.
non-disclosure agreement required analog-to-digital converter (adc) advance information MC68HC708AS48 rev. 4.0 326 analog-to-digital converter (adc) motorola table 19-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptd0/atd8 01001 ptd1/atd9 01010 ptd2/atd10 01011 ptd3/atd11 01100 ptd4/atd12 01101 ptd5/atd13 01110 ptd6/atd14/tclk 01111 ptd7/atd15 (see note 3) range 10000 ($10) to 11010 ($1a) unused (see note 1) 11011 reserved 1 1 1 0 0 v ddaref /v dda (see note 2) 1 1 1 0 1 v refh (see note 2) 1 1 1 1 0 v ssa /v refl (see note 2) 1 1 1 1 1 [adc power off] notes: 1. if any unused channels are selected, the resulting adc conversion will be unknown. 2. the voltage levels supplied from internal reference nodes as speci?ed in the table are used to verify the operation of the adc converter both in production test and for user applications. 3. this channel is only available in the 64-pin qfp package.
analog-to-digital converter (adc) i/o registers MC68HC708AS48 rev. 4.0 advance information motorola analog-to-digital converter (adc) 327 non-disclosure agreement required 19.8.2 adc data register one 8-bit result register is provided. this register is updated each time an adc conversion completes. 19.8.3 adc input clock register this register selects the clock frequency for the adc. adiv2:adiv0 adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 19-2 shows the available clock configurations. the adc clock should be set to approximately 1 mhz. address: $0039 bit 7 654321 bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: rrrrrrrr reset: indeterminate after reset r = reserved figure 19-3. adc data register (adr) address: $003a bit 7 654321 bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: rrrr reset: 0 0000000 r = reserved figure 19-4. adc input clock register (adiclk)
non-disclosure agreement required analog-to-digital converter (adc) advance information MC68HC708AS48 rev. 4.0 328 analog-to-digital converter (adc) motorola adiclk adc input clock register bit adiclk selects either bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. (see 21.7 adc characteristics .) 1 = internal bus clock 0 = external clock (cgmxclk) note: during the conversion process, changing the adc clock will result in an incorrect conversion. table 19-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock /1 0 0 1 adc input clock / 2 0 1 0 adc input clock / 4 0 1 1 adc input clock / 8 1 x x adc input clock / 16 x = dont care f xclk or bus frequency 1 mhz = ??????????? adiv[2:0]
MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 329 non-disclosure agreement required advance information MC68HC708AS48 section 20. byte data link controllerCdigital (bdlcCd) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 20.4.1 bdlc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . .334 20.4.1.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 20.4.1.2 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 20.4.1.3 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 20.4.1.4 bdlc wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 20.4.1.5 bdlc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 20.4.1.6 digital loopback mode. . . . . . . . . . . . . . . . . . . . . . . . . .336 20.4.1.7 analog loopback mode . . . . . . . . . . . . . . . . . . . . . . . . .336 20.5 bdlc mux interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 20.5.1 rx digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 20.5.1.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 20.5.1.2 performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 20.5.2 j1850 frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 20.5.3 j1850 vpw symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 20.5.4 j1850 vpw valid/invalid bits and symbols . . . . . . . . . . .346 20.5.5 message arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 20.6 bdlc protocol handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 20.6.1 protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 20.6.2 rx and tx shift registers . . . . . . . . . . . . . . . . . . . . . . . . .353 20.6.3 rx and tx shadow registers . . . . . . . . . . . . . . . . . . . . . .354 20.6.4 digital loopback multiplexer . . . . . . . . . . . . . . . . . . . . . . .354 20.6.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.6.5.1 4x mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.6.5.2 receiving a message in block mode . . . . . . . . . . . . . . .355 20.6.5.3 transmitting a message in block mode . . . . . . . . . . . . .355
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 330 byte data link controllerCdigital (bdlcCd) motorola 20.6.5.4 j1850 bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.6.5.5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 20.7 bdlc cpu interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20.7.1 bdlc analog and roundtrip delay. . . . . . . . . . . . . . . . . .358 20.7.2 bdlc control register 1. . . . . . . . . . . . . . . . . . . . . . . . . .360 20.7.3 bdlc control register 2. . . . . . . . . . . . . . . . . . . . . . . . . .363 20.7.4 bdlc state vector register . . . . . . . . . . . . . . . . . . . . . . .371 20.7.5 bdlc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
byte data link controllerCdigital (bdlcCd) introduction MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 331 non-disclosure agreement required 20.2 introduction the byte data link controller (bdlc) provides access to an external serial communication multiplex bus, operating according to the sae j1850 protocol. 20.3 features features of the bdlc module include: ? sae j1850 class b data communications network interface compatible and iso compatible for low-speed ( <125 kbps) serial data communications in automotive applications ? 10.4-kbps variable pulse width (vpw) bit format ? digital noise filter ? collision detection ? hardware cyclical redundancy check (crc) generation and checking ? two power-saving modes with automatic wakeup on network activity ? polling or cpu interrupts ? block mode receive and transmit supported ? 4x receive mode, 41.6 kbps, supported ? digital loopback mode ? analog loopback mode ? in-frame response (ifr) types 0, 1, 2, and 3 supported
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 332 byte data link controllerCdigital (bdlcCd) motorola 20.4 functional description figure 20-1 shows the organization of the bdlc module. the cpu interface contains the software addressable registers and provides the link between the cpu and the buffers. the buffers provide storage for data received and data to be transmitted onto the j1850 bus. the protocol handler is responsible for the encoding and decoding of data bits and special message symbols during transmission and reception. the mux interface provides the link between the bdlc digital section and the analog physical interface. the wave shaping, driving, and digitizing of data is performed by the physical interface. use of the bdlc module in message networking fully implements the sae standard j1850 class b data communication network interface specification. note: it is recommended that the reader be familiar with the sae j1850 document and iso serial communication document prior to proceeding with this section of the mc68hc08as20 specification. figure 20-1. bdlc block diagram . cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
byte data link controllerCdigital (bdlcCd) functional description MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 333 non-disclosure agreement required addr. name bit 7 6 5 4 3 2 1 bit 0 $003b bdlc analog and roundtrip delay register (bard) see page 358. read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset: 1 1 0 0 0 1 1 1 $003c bdlc control register 1 (bcr1) see page 360. read: imsg clks r1 r0 00 ie wcm write: r r reset: 1 1 1 0 0 0 0 0 $003d bdlc control register 2 (bcr2) see page 363. read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset: 1 1 0 0 0 0 0 0 $003e bdlc state vector register (bsvr) see page 371. read: 0 0 i3 i2 i1 i0 0 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $003f bdlc data register (bdr) see page 373. read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: undetermined after reset r = reserved figure 20-2. bdlc input/output (i/o) register summary
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 334 byte data link controllerCdigital (bdlcCd) motorola 20.4.1 bdlc operating modes the bdlc has five main modes of operation which interact with the power supplies, pins, and rest of the mcu as shown in figure 20-3 . figure 20-3. bdlc operating modes state diagram 20.4.1.1 power off mode for the bdlc to guarantee operation, this mode is entered from reset mode whenever the bdlc supply voltage, v dd , drops below its minimum specified value. the bdlc will be placed in reset mode by low-voltage reset (lvr) before being powered down. in power off mode, the pin input and output specifications are not guaranteed. v dd > v dd (minimum) and power off reset bdlc stop run v dd v dd (minimum) stop instruction or from any mode bdlc wait network activity or wait instruction and wcm = 1 wait instruction and wcm = 0 any mcu reset source asserted no mcu reset source asserted any mcu reset source asserted network activity or other mcu wakeup other mcu wakeup (cop, illaddr, pu, reset, lvr, por)
byte data link controllerCdigital (bdlcCd) functional description MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 335 non-disclosure agreement required 20.4.1.2 reset mode this mode is entered from power off mode whenever the bdlc supply voltage, v dd , rises above its minimum specified value (v dd C10%) and some mcu reset source is asserted. the internal mcu reset must be asserted while powering up the bdlc or an unknown state will be entered and correct operation cannot be guaranteed. reset mode is also entered from any other mode as soon as one of the mcus possible reset sources (such as lvr, por, cop watchdog, reset pin, etc.) is asserted. in reset mode, the internal bdlc voltage references are operative, v dd is supplied to the internal circuits which are held in their reset state, and the internal bdlc system clock is running. registers will assume their reset condition. because outputs are held in their programmed reset state, inputs and network activity are ignored. 20.4.1.3 run mode this mode is entered from reset mode after all mcu reset sources are no longer asserted. run mode is entered from the bdlc wait mode whenever activity is sensed on the j1850 bus. run mode is entered from the bdlc stop mode whenever network activity is sensed, although messages will not be received properly until the clocks have stabilized and the cpu is also in run mode. in this mode, normal network operation takes place. the user should ensure that all bdlc transmissions have ceased before exiting this mode. 20.4.1.4 bdlc wait mode this power-conserving mode is entered automatically from run mode whenever the cpu executes a wait instruction and if the wcm bit in the bcr1 register is cleared previously. in this mode, the bdlc internal clocks continue to run. the first passive-to-active transition of the bus generates a cpu interrupt request from the bdlc, which wakes up the bdlc and the cpu. in addition, if
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 336 byte data link controllerCdigital (bdlcCd) motorola the bdlc receives a valid end-of-frame (eof) symbol while operating in wait mode, then the bdlc also will generate a cpu interrupt request, which wakes up the bdlc and the cpu. see 20.8.1 wait mode . 20.4.1.5 bdlc stop mode this power-conserving mode is entered automatically from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait instruction and the wcm bit in the bcr1 ($003e) is set previously. in this mode, the bdlc internal clocks are stopped but the physical interface circuitry is placed in a low-power mode and awaits network activity. if network activity is sensed, then a cpu interrupt request will be generated, restarting the bdlc internal clocks. see 20.8.2 stop mode . 20.4.1.6 digital loopback mode when a bus fault has been detected, the digital loopback mode is used to determine if the fault condition is caused by failure in the nodes internal circuits or elsewhere in the network, including the nodes analog physical interface. in this mode, the transmit digital output pin (bdtxd) and the receive digital input pin (bdrxd) of the digital interface are disconnected from the analog physical interface and tied together to allow the digital portion of the bdlc to transmit and receive its own messages without driving the j1850 bus. 20.4.1.7 analog loopback mode analog loopback mode is used to determine if a bus fault has been caused by a failure in the nodes off-chip analog transceiver or elsewhere in the network. the bcld analog loopback mode does not modify the digital transmit or receive functions of the bdlc. it does, however, ensure that once analog loopback mode is exited, the bdlc will wait for an idle bus condition before participation in network communication resumes. if the off-chip analog transceiver has a loopback mode, it usually causes the input to the output drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted without driving the j1850 bus. in this mode, the output
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 337 non-disclosure agreement required to the j1850 bus typically is high impedance. this allows the communication path through the analog transceiver to be tested without interfering with network activity. using the bdlc analog loopback mode in conjunction with the analog transceivers loopback mode ensures that, once the off-chip analog transceiver has exited loopback mode, the bcld will not begin communicating before a known condition exists on the j1850 bus. 20.5 bdlc mux interface the mux interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface. figure 20-4. bdlc block diagram cpu interface to j1850 bus mux interface protocol handler physical interface bdlc to cpu
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 338 byte data link controllerCdigital (bdlcCd) motorola 20.5.1 rx digital filter the receiver section of the bdlc includes a digital low pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown in figure 20-5 . figure 20-5. bdlc rx digital filter block diagram 20.5.1.1 operation the clock for the digital filter is provided by the mux interface clock (see f bdlc parameter in table 20-3 ). at each positive edge of the clock signal, the current state of the receiver physical interface (bdrxd) signal is sampled. the bdrxd signal state is used to determine whether the counter should increment or decrement at the next negative edge of the clock signal. the counter will increment if the input data sample is high but decrement if the input sample is low. therefore, the counter will thus progress either up toward 15 if, on average, the bdrxd signal remains high or progress down toward 0 if, on average, the bdrxd signal remains low. when the counter eventually reaches the value 15, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the counter is prevented from overflowing and can be decremented only from this state. 4-bit up/down counter data latch up/ down out filtered rx data out mux input sync dq rx data from physical interface clock (bdrxd) dq interface
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 339 non-disclosure agreement required alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 0 and the data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, the counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the signal. 20.5.1.2 performance the performance of the digital filter is best described in the time domain rather than the frequency domain. if the signal on the bdrxd signal transitions, then there will be a delay before that transition appears at the filtered rx data output signal. this delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. this filter delay must be taken into account when performing message arbitration. for example, if the frequency of the mux interface clock (f bdlc ) is 1.0486 mhz, then the period (t bdlc ) is 954 ns and the maximum filter delay in the absence of noise will be 15.259 m s. the effect of random noise on the bdrxd signal depends on the characteristics of the noise itself. narrow noise pulses on the bdrxd signal will be ignored completely if they are shorter than the filter delay. this provides a degree of low pass filtering. if noise occurs during a symbol transition, the detection of that transition can be delayed by an amount equal to the length of the noise burst. this is just a reflection of the uncertainty of where the transition is truly occurring within the noise. noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length, will be detected by the next stage of the bdlcs receiver as an invalid symbol. noise pulses that are longer than the shortest allowable symbol length will be detected normally as an invalid symbol or as invalid data when the frames crc is checked.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 340 byte data link controllerCdigital (bdlcCd) motorola 20.5.2 j1850 frame format all messages transmitted on the j1850 bus are structured using the format shown in figure 20-6 . j1850 states that each message has a maximum length of 101 pwm bit times or 12 vpw bytes, excluding sof, eod, nb, and eof, with each byte transmitted most significant bit (msb) first. all vpw symbol lengths described here are typical values at a 10.4-kbps bit rate. sof start-of-frame symbol all messages transmitted onto the j1850 bus must begin with a long-active 200 m s period sof symbol. this indicates the start of a new message transmission. the sof symbol is not used in the crc calculation. data in-message data bytes the data bytes contained in the message include the message priority/type, message id byte (typically the physical address of the responder), and any actual data being transmitted to the receiving node. the message format used by the bdlc is similar to the 3-byte consolidated header message format outlined by the sae j1850 document. see sae j1850 class b data communications network interface for more information about 1- and 3-byte headers. messages transmitted by the bdlc onto the j1850 bus must contain at least one data byte, and, therefore, can be as short as one data byte and one crc byte. each data byte in the message is eight bits in length and is transmitted msb to lsb (least significant bit). data e o d optional i f s idle sof priority (data0) message id (data1) data n crc n b ifr eof idle figure 20-6. j1850 bus message format (vpw)
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 341 non-disclosure agreement required crc cyclical redundancy check byte this byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message. the bdlc calculates the crc byte and appends it onto any messages transmitted onto the j1850 bus. it also performs crc detection on any messages it receives from the j1850 bus. crc generation uses the divisor polynomial x 8 + x 4 + x 3 + x 2 + 1. the remainder polynomial initially is set to all ones. each byte in the message after the start-of-frame (sof) symbol is processed serially through the crc generation circuitry. the ones complement of the remainder then becomes the 8-bit crc byte, which is appended to the message after the data bytes, in msb-to-lsb order. when receiving a message, the bdlc uses the same divisor polynomial. all data bytes, excluding the sof and end of data symbols (eod) but including the crc byte, are used to check the crc. if the message is error free, the remainder polynomial will equal x 7 +x 6 +x 2 = $c4, regardless of the data contained in the message. if the calculated crc does not equal $c4, the bdlc will recognize this as a crc error and set the crc error flag in the bsvr ($003e). eod end-of-data symbol the eod symbol is a long 200- m s passive period on the j1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. no flag is set upon reception of the eod symbol. ifr in-frame response bytes the ifr section of the j1850 message format is optional. users desiring further definition of in-frame response should review the sae j1850 class b data communications network interface specification. eof end-of-frame symbol this symbol is a long 280- m s passive period on the j1850 bus and is longer than an end-of-data (eod) symbol, which signifies the end of a message. since an eof symbol is longer than a 200- m s eod
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 342 byte data link controllerCdigital (bdlcCd) motorola symbol, if no response is transmitted after an eod symbol, it becomes an eof, and the message is assumed to be completed. the eof flag is set upon receiving the eof symbol. ifs inter-frame separation symbol the ifs symbol is a 20- m s passive period on the j1850 bus which allows proper synchronization between nodes during continuous message transmission. the ifs symbol is transmitted by a node after the completion of the end-of-frame (eof) period and, therefore is seen as a 300- m s passive period. when the last byte of a message has been transmitted onto the j1850 bus and the eof symbol time has expired, all nodes then must wait for the ifs symbol time to expire before transmitting a start-of-frame (sof) symbol, marking the beginning of another message. however, if the bdlc is waiting for the ifs period to expire before beginning a transmission and a rising edge is detected before the ifs time has expired, it will synchronize internally to that edge. a rising edge may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, causing different nodes to observe the completion of the ifs period at different times. to allow for individual clock tolerances, receivers must synchronize to any sof occurring during an ifs period. break break the bdlc cannot transmit a break symbol. if the bdlc is transmitting at the time a break is detected, it treats the break as if a transmission error had occurred and halts transmission. if the bdlc detects a break symbol while receiving a message, it treats the break as a reception error and sets the invalid symbol flag in the bsvr, also ignoring the frame it was receiving. if while receiving a message in 4x mode, the bdlc detects a break symbol, it treats the break as a reception error, sets the invalid symbol flag, and exits 4x mode (the rx4xe bit in bcr2 is cleared automatically). if bus control is required after the break symbol is received and the ifs time has elapsed, the programmer must resend the transmission byte using highest priority.
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 343 non-disclosure agreement required note: the j1850 protocol break symbol is not related to the hc08 break module (see section 11. break module (break) .) idle idle bus an idle condition exists on the bus during any passive period after expiration of the ifs period (for example, > 300 m s). any node sensing an idle bus condition can begin transmission immediately. 20.5.3 j1850 vpw symbols huntsingers variable pulse width modulation (vpw) is an encoding technique in which each bit is defined by the time between successive transitions and by the level of the bus between transitions, (for instance, active or passive). active and passive bits are used alternately. this encoding technique is used to reduce the number of bus transitions for a given bit rate. each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one of two lengths, either 64 m s or 128 m s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the start-of-frame (sof), end-of-data (eod), end-of-frame (eof), and inter-frame separation (ifs) symbols always will be encoded at an assigned level and length. see figure 20-7 . each message will begin with an sof symbol, an active symbol, and, therefore, each data byte (including the crc byte) will begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. all vpw bit lengths stated here are typical values at a 10.4-kbps bit rate. eof, eod, ifs, and idle, however, are not driven j1850 bus states. they are passive bus periods observed by each nodes cpu.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 344 byte data link controllerCdigital (bdlcCd) motorola logic 0 a logic 0 is defined as either: C an active-to-passive transition followed by a passive period 64 m s in length, or C a passive-to-active transition followed by an active period 128 m s in length see figure 20-7 (a) . figure 20-7. j1850 vpw symbols with nominal symbol times 128 m s active passive 64 m s or (a) logic 0 128 m s active passive 64 m s or ( b) logic 1 200 m s active passive ( d) start of frame active passive (f) end of frame 3 240 m s (c) break 200 m s ( e) end of data 280 m s (g) inter-frame 20 m s 300 m s idle > 300 m s (h) idle separation
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 345 non-disclosure agreement required logic 1 a logic 1 is defined as either: C an active-to-passive transition followed by a passive period 128 m s in length, or C a passive-to-active transition followed by an active period 64 m s in length see figure 20-7 (b) . normalization bit (nb) the nb symbol has the same property as a logic 1 or a logic 0. it is only used in ifr message responses. break signal (break) the break signal is defined as a passive-to-active transition followed by an active period of at least 240 m s (see figure 20-7 (c) ). start-of-frame symbol (sof) the sof symbol is defined as passive-to-active transition followed by an active period 200 m s in length (see figure 20-7 (d) ). this allows the data bytes which follow the sof symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. end-of-data symbol (eod) the eod symbol is defined as an active-to-passive transition followed by a passive period 200 m s in length (see figure 20-7 (e) ). end-of-frame symbol (eof) the eof symbol is defined as an active-to-passive transition followed by a passive period 280 m s in length (see figure 20-7 (f) ). if no ifr byte is transmitted after an eod symbol is transmitted, after another 80 m s the eod becomes an eof, indicating completion of the message. inter-frame separation symbol (ifs) the ifs symbol is defined as a passive period 300 m s in length. the 20- m s ifs symbol contains no transition, since when it is used it always appends to a 280- m s eof symbol (see figure 20-7 (g) ).
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 346 byte data link controllerCdigital (bdlcCd) motorola idle an idle is defined as a passive period greater than 300 m s in length. 20.5.4 j1850 vpw valid/invalid bits and symbols the timing tolerances for receiving data bits and symbols from the j1850 bus have been defined to allow for variations in oscillator frequencies. in many cases, the maximum time allowed to define a data bit or symbol is equal to the minimum time allowed to define another data bit or symbol. since the minimum resolution of the bdlc for determining what symbol is being received is equal to a single period of the mux interface clock (t bdlc ), an apparent separation in these maximum time/minimum time concurrences equals one cycle of t bdlc . this one clock resolution allows the bdlc to differentiate properly between the different bits and symbols. this is done without reducing the valid window for receiving bits and symbols from transmitters onto the j1850 bus, which has varying oscillator frequencies. in huntsingers variable pulse width (vpw) modulation bit encoding, the tolerances for both the passive and active data bits received and the symbols received are defined with no gaps between definitions. for example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1, and the maximum length of an active logic 0 is equal to the minimum length of a valid sof symbol. invalid passive bit see figure 20-8 (1) . if the passive-to-active received transition beginning the next data bit or symbol occurs between the active-to-passive transition beginning the current data bit (or symbol) and a , the current bit would be invalid.
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 347 non-disclosure agreement required figure 20-8. j1850 vpw received passive symbol times valid passive logic 0 see figure 20-8 (2) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 0. valid passive logic 1 see figure 20-8 (3) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 1. valid eod symbol see figure 20-8 (4) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid end-of-data symbol (eod). a bc b a (1) invalid passive bit (2) valid passive logic 0 (3) valid passive logic 1 64 m s 128 m s cd (4) valid eod symbol 200 m s active passive active passive active passive active passive
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 348 byte data link controllerCdigital (bdlcCd) motorola figure 20-9. j1850 vpw received passive eof and ifs symbol times valid eof and ifs symbols in figure 20-9 (1) , if the passive-to-active received transition beginning the sof symbol of the next message occurs between a and b , the current symbol will be considered a valid end-of-frame (eof) symbol. see figure 20-9 (2) . if the passive-to-active received transition beginning the sof symbol of the next message occurs between c and d , the current symbol will be considered a valid eof symbol followed by a valid inter-frame separation symbol (ifs). all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, due to variations in clock frequencies and bus loading, some nodes may recognize a valid ifs symbol before others and immediately begin transmitting. therefore, any time a node waiting to transmit detects a passive-to-active transition once a valid eof has been detected, it should immediately begin transmission, initiating the arbitration process. idle bus in figure 20-9 (2) , if the passive-to-active received transition beginning the start-of-frame (sof) symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. cd (2) valid eof+ 280 m s 300 m s a b ( 1) valid eof symbol active passive active passive ifs symbol
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 349 non-disclosure agreement required figure 20-10. j1850 vpw received active symbol times invalid active bit in figure 20-10 (1) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between the passive-to-active transition beginning the current data bit (or symbol) and a , the current bit would be invalid. valid active logic 1 in figure 20-10 (2) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 1. valid active logic 0 in figure 20-10 (3) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 0. a bc b a (1) invalid active bit (2) valid active logic 1 (3) valid active logic 0 64 m s 128 m s cd (4) valid sof symbol 200 m s active passive active passive active passive active passive
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 350 byte data link controllerCdigital (bdlcCd) motorola valid sof symbol in figure 20-10 (4) , if the active-to-passive received transition beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid sof symbol. valid break symbol in figure 20-11 , if the next active-to-passive received transition does not occur until after e , the current symbol will be considered a valid break symbol. a break symbol should be followed by a start-of-frame (sof) symbol beginning the next message to be transmitted onto the j1850 bus. see 20.5.2 j1850 frame format for bdlc response to break symbols. figure 20-11. j1850 vpw received break symbol times 20.5.5 message arbitration message arbitration on the j1850 bus is accomplished in a non-destructive manner, allowing the message with the highest priority to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. if the bdlc wants to transmit onto the j1850 bus, but detects that another message is in progress, it waits until the bus is idle. however, if multiple nodes begin to transmit in the same synchronization window, message arbitration will occur beginning with the first bit after the sof symbol and continue with each bit thereafter. if a write to the bdr ($003f) (for instance, to initiate transmission) occurred on or before 104 ? t bdlc from the received rising edge, then the bdlc will transmit (2) valid break symbol 240 m s e active passive
byte data link controllerCdigital (bdlcCd) bdlc mux interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 351 non-disclosure agreement required and arbitrate for the bus. if a cpu write to the bdr occurred after 104 ? t bdlc from the detection of the rising edge, then the bdlc will not transmit, but will wait for the next ifs period to expire before attempting to transmit the byte. the variable pulse width modulation (vpw) symbols and j1850 bus electrical characteristics are chosen carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive type) simultaneously transmitted. hence, logic 0s are said to be dominant and logic 1s are said to be recessive. whenever a node detects a dominant bit on bdrxd when it transmitted a recessive bit, it loses arbitration and immediately stops transmitting. this is known as bitwise arbitration. since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and will always win arbitration. for instance, a message with priority 000 will win arbitration over a message with priority 011. this method of arbitration will work no matter how many bits of priority encoding are contained in the message. figure 20-12. j1850 vpw bitwise arbitrations transmitter a transmitter b j1850 bus sof data bit 1 data bit 4 data bit 5 0 transmitter a detects an active state on the bus and stops transmitting transmitter b wins passive active passive active passive active 0 0 1 1 1 data bit 2 1 1 1 data bit 3 0 0 0 0 1 arbitration and continues transmitting
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 352 byte data link controllerCdigital (bdlcCd) motorola during arbitration, or even throughout the transmitting message, when an opposite bit is detected, transmission is stopped immediately unless it occurs on the 8th bit of a byte. in this case, the bdlc automatically will append up to two extra logic 1 bits and then stop transmitting. these two extra bits will be arbitrated normally and thus will not interfere with another message. the second logic 1 bit will not be sent if the first loses arbitration. if the bdlc has lost arbitration to another valid message, then the two extra logic 1s will not corrupt the current message. however, if the bdlc has lost arbitration due to noise on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored as a noise-corrupted message. 20.6 bdlc protocol handler the protocol handler is responsible for framing, arbitration, crc generation/checking, and error detection. the protocol handler conforms to sae j1850 class b data communications network interface . note: motorola assumes that the reader is familiar with the j1850 specification before reading this protocol handler description. figure 20-13. bdlc block diagram to cpu cpu interface to j1850 bus mux interface protocol handler physical interface bdlc
byte data link controllerCdigital (bdlcCd) bdlc protocol handler MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 353 non-disclosure agreement required 20.6.1 protocol architecture the protocol handler contains the state machine, rx shadow register, tx shadow register, rx shift register, tx shift register, and loopback multiplexer as shown in figure 20-14 . figure 20-14. bdlc protocol handler outline 20.6.2 rx and tx shift registers the rx shift register gathers received serial data bits from the j1850 bus and makes them available in parallel form to the rx shadow register. the tx shift register takes data, in parallel form, from the tx shadow register and presents it serially to the state machine so that it can be transmitted onto the j1850 bus. rx shift register to cpu interface and rx/tx buffers state machine to physical interface rx data tx data control 8 tx shift register bdtxd rxd control 8 rx shadow register tx shadow register loopback bdrxd bdtxd multiplexer dloop from bcr2 aloop loopback control
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 354 byte data link controllerCdigital (bdlcCd) motorola 20.6.3 rx and tx shadow registers immediately after the rx shift register has completed shifting in a byte of data, this data is transferred to the rx shadow register and rdrf or rxifr is set (see 20.7.4 bdlc state vector register ). an interrupt is generated if the interrupt enable bit (ie) in bcr1 is set. after the transfer takes place, this new data byte in the rx shadow register is available to the cpu interface, and the rx shift register is ready to shift in the next byte of data. data in the rx shadow register must be retrieved by the cpu before it is overwritten by new data from the rx shift register. once the tx shift register has completed its shifting operation for the current byte, the data byte in the tx shadow register is loaded into the tx shift register. after this transfer takes place, the tx shadow register is ready to accept new data from the cpu when the tdre flag in the bsvr is set. 20.6.4 digital loopback multiplexer the digital loopback multiplexer connects rxd to either bdtxd or bdrxd, depending on the state of the dloop bit in the bcr2 ($003d) (see 20.7.3 bdlc control register 2 ). 20.6.5 state machine all functions associated with performing the protocol are executed or controlled by the state machine. the state machine is responsible for framing, collision detection, arbitration, crc generation/checking, and error detection. these subsections describe the bdlcs actions in a variety of situations. 20.6.5.1 4x mode the bdlc can exist on the same j1850 bus as modules which use a special 4x (41.6 kbps) mode of j1850 variable pulse width modulation (vpw) operation. the bdlc cannot transmit in 4x mode, but it can receive messages in 4x mode, if the rx4x bit is set in bcr2. if the
byte data link controllerCdigital (bdlcCd) bdlc protocol handler MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 355 non-disclosure agreement required rx4x bit is not set in the bcr2, any 4x message on the j1850 bus is treated as noise by the bdlc and is ignored. 20.6.5.2 receiving a message in block mode although not a part of the sae j1850 protocol, the bdlc does allow for a special block mode of operation of the receiver. as far as the bdlc is concerned, a block mode message is simply a long j1850 frame that contains an indefinite number of data bytes. all other features of the frame remain the same, including the sof, crc, and eod symbols. another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. this is usually accomplished by sending a special predefined message. 20.6.5.3 transmitting a message in block mode a block mode message is transmitted inherently by simply loading the bytes one by one into the bdr until the message is complete. the programmer should wait until the tdre flag (see 20.7.4 bdlc state vector register ) is set prior to writing a new byte of data into the bdr. the bdlc does not contain any predefined maximum j1850 message length requirement. 20.6.5.4 j1850 bus errors the bdlc detects several types of transmit and receive errors which can occur during the transmission of a message onto the j1850 bus. transmission error if the message transmitted by the bdlc contains invalid bits or framing symbols on non-byte boundaries, this constitutes a transmission error. when a transmission error is detected, the bdlc immediately will cease transmitting. the error condition ($1c) is reflected in the bsvr (see table 20-5 ). if the interrupt enable bit (ie in bcr1) is set, a cpu interrupt request from the bdlc is generated.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 356 byte data link controllerCdigital (bdlcCd) motorola crc error a cyclical redundancy check (crc) error is detected when the data bytes and crc byte of a received message are processed and the crc calculation result is not equal. the crc code will detect any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. the crc error flag ($18 in bsvr) is set when a crc error is detected. (see 20.7.4 bdlc state vector register .) symbol error a symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the j1850 bus. the ($1c) invalid symbol is set when a symbol error is detected. (see 20.7.4 bdlc state vector register .) framing error a framing error is detected if an eod or eof symbol is detected on a non-byte boundary from the j1850 bus. a framing error also is detected if the bdlc is transmitting the eod and instead receives an active symbol. the ($1c) symbol invalid, or the out-of-range flag, is set when a framing error is detected. (see 20.7.4 bdlc state vector register .) bus fault if a bus fault occurs, the response of the bdlc will depend upon the type of bus fault. if the bus is shorted to battery, the bdlc will wait for the bus to fall to a passive state before it will attempt to transmit a message. as long as the short remains, the bdlc will never attempt to transmit a message onto the j1850 bus. if the bus is shorted to ground, the bdlc will see an idle bus, begin to transmit the message, and then detect a transmission error ($1c in bsvr), since the short to ground would not allow the bus to be driven to the active (dominant) sof state. the bdlc will abort that transmission and wait for the next cpu command to transmit.
byte data link controllerCdigital (bdlcCd) bdlc protocol handler MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 357 non-disclosure agreement required in any case, if the bus fault is temporary, as soon as the fault is cleared, the bdlc will resume normal operation. if the bus fault is permanent, it may result in permanent loss of communication on the j1850 bus. (see 20.7.4 bdlc state vector register .) break break if a break symbol is received while the bdlc is transmitting or receiving, an invalid symbol ($1c in bsvr) interrupt will be generated. reading the bsvr ($0003e) (see 20.7.4 bdlc state vector register ) will clear this interrupt condition. the bdlc will wait for the bus to idle, then wait for a start-of-frame (sof) symbol. the bdlc cannot transmit a break symbol. it only can receive a break symbol from the j1850 bus. 20.6.5.5 summary table 20-1. bdlc j1850 bus error summary error condition bdlc function transmission error for invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt will be generated. bdlc stops transmission. cyclical redundancy check (crc) error crc error interrupt will be generated. the bdlc will wait for eof. invalid symbol: bdlc transmits, but receives invalid bits (noise) the bdlc will abort transmission immediately. invalid symbol interrupt will be generated. framing error invalid symbol interrupt will be generated. the bdlc will wait for end-of-frame (eof). bus short to v dd the bdlc will not transmit until the bus is idle. invalid symbol interrupt will be generated. eof interrupt also must be seen before another transmission attempt. depending on length of the short, loa ?ag also may be set. bus short to gnd thermal overload will shut down physical interface. fault condition is seen as invalid symbol ?ag. eof interrupt must also be seen before another transmission attempt. bdlc receives break symbol invalid symbol interrupt will be generated. the bdlc will wait for the next valid sof.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 358 byte data link controllerCdigital (bdlcCd) motorola 20.7 bdlc cpu interface the cpu interface provides the interface between the cpu and the bdlc and consists of five user registers. figure 20-15. bdlc block diagram 20.7.1 bdlc analog and roundtrip delay this register programs the bdlc to compensate for various delays of different external transceivers. the default delay value is 16 m s. timing adjustments from 9 m sto24 m s in steps of 1 m s are available. the bard register can be written only once after each reset, after which they become read-only bits. the register may be read at any time. cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc address: $003b bit 7 654321 bit 0 read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset: 11000111 r = reserved figure 20-16. bdlc analog and roundtrip delay register (bard)
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 359 non-disclosure agreement required ate analog transceiver enable bit the analog transceiver enable (ate) bit is used to select either the on-board or an off-chip analog transceiver. 1 = select on-board analog transceiver 0 = select off-chip analog transceiver note: this device does not contain an on-board transceiver. this bit should be programmed to a logic 0 for proper operation. rxpol receive pin polarity bit the receive pin polarity (rxpol) bit is used to select the polarity of an incoming signal on the receive pin. some external analog transceivers invert the receive signal from the j1850 bus before feeding it back to the digital receive pin. 1 = select normal/true polarity; true non-inverted signal from the j1850 bus; for example, the external transceiver does not invert the receive signal 0 = select inverted polarity, where an external transceiver inverts the receive signal from the j1850 bus bo3Cbo0 bard offset bits table 20-2 shows the expected transceiver delay with respect to bard offset values.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 360 byte data link controllerCdigital (bdlcCd) motorola 20.7.2 bdlc control register 1 this register is used to configure and control the bdlc. table 20-2. bdlc transceiver delay bard offset bits bo[3:0] corresponding expected transceivers delays ( m s) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 address: $003c bit 7 654321 bit 0 read: imsg clks r1 r0 00 ie wcm write: r r reset: 11100000 r = reserved figure 20-17. bdlc control register 1 (bcr1)
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 361 non-disclosure agreement required imsg ignore message bit this bit is used to disable the receiver until a new start-of-frame (sof) is detected. 1 = disable receiver. when set, all bdlc interrupt requests will be masked (except $20 in bsvr) and the status bits will be held in their reset state. if this bit is set while the bdlc is receiving a message, the rest of the incoming message will be ignored. 0 = enable receiver. this bit is cleared automatically by the reception of an sof symbol or a break symbol. it will then generate interrupt requests and will allow changes of the status register to occur. however, these interrupts may still be masked by the interrupt enable (ie) bit. clks clock bit for j1850 bus communications to take place, the nominal bdlc operating frequency (f bdlc ) must always be 1.048576 mhz or 1 mhz. the clks register bit allows the user to select the frequency (1.048576 mhz or 1 mhz) used to automatically adjust symbol timing. 1 = binary frequency (1.048576 mhz) selected for f bdlc 0 = integer frequency (1 mhz) selected for f bdlc r1 and r0 rate select bits these bits determine the amount by which the frequency of the mcu cgmxclk signal is divided to form the mux interface clock (f bdlc ) which defines the basic timing resolution of the mux interface. they may be written only once after reset, after which they become read-only bits. the nominal frequency of f bdlc must always be 1.048576 mhz or 1.0 mhz for j1850 bus communications to take place. hence, the value programmed into these bits is dependent on the chosen mcu system clock frequency per table 20-3 .
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 362 byte data link controllerCdigital (bdlcCd) motorola ie interrupt enable bit this bit determines whether the bdlc will generate cpu interrupt requests in run mode. it does not affect cpu interrupt requests when exiting the bdlc stop or bdlc wait modes. interrupt requests will be maintained until all of the interrupt request sources are cleared by performing the specified actions upon the bdlcs registers. interrupts that were pending at the time that this bit is cleared may be lost. 1 = enable interrupt requests from bdlc 0 = disable interrupt requests from bdlc if the programmer does not wish to use the interrupt capability of the bdlc, the bdlc state vector register (bsvr) can be polled periodically by the programmer to determine bdlc states. see 20.7.4 bdlc state vector register for a description of the bsvr. wcm wait clock mode bit this bit determines the operation of the bdlc during cpu wait mode. see 20.8.2 stop mode and 20.8.1 wait mode for more details on its use. 1 = stop bdlc internal clocks during cpu wait mode 0 = run bdlc internal clocks during cpu wait mode table 20-3. bdlc rate selection f xclk frequency r1 r0 division f bdlc 1.049 mhz 0 0 1 1.049 mhz 2.097 mhz 0 1 2 1.049 mhz 4.194 mhz 1 0 4 1.049 mhz 8.389 mhz 1 1 8 1.049 mhz 1.000 mhz 0 0 1 1.00 mhz 2.000 mhz 0 1 2 1.00 mhz 4.000 mhz 1 0 4 1.00 mhz 8.000 mhz 1 1 8 1.00 mhz
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 363 non-disclosure agreement required 20.7.3 bdlc control register 2 this register controls transmitter operations of the bdlc. it is recommended that bset and bclr instructions be used to manipulate data in this register to ensure that the registers content does not change inadvertently. aloop analog loopback mode bit this bit determines whether the j1850 bus will be driven by the analog physical interfaces final drive stage. the programmer can use this bit to reset the bdlc state machine to a known state after the off-chip analog transceiver is placed in loopback mode. when the user clears aloop, to indicate that the off-chip analog transceiver is no longer in loopback mode, the bdlc waits for an eof symbol before attempting to transmit. most transceivers have the aloop feature available. 1 = input to the analog physical interfaces final drive stage is looped back to the bdlc receiver. the j1850 bus is not driven. 0 = the j1850 bus will be driven by the bdlc. after the bit is cleared, the bdlc requires the bus to be idle for a minimum of end-of-frame symbol time (t trv4 ) before message reception or a minimum of inter-frame symbol time (t trv6 ) before message transmission. (see 21.15 bdlc receiver vpw symbol timings .) address: $003d bit 7 654321 bit 0 read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset: 11000000 figure 20-18. bdlc control register 2 (bcr2)
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 364 byte data link controllerCdigital (bdlcCd) motorola dloop digital loopback mode bit this bit determines the source to which the digital receive input (bdrxd) is connected and can be used to isolate bus fault conditions (see figure 20-14 ). if a fault condition has been detected on the bus, this control bit allows the programmer to connect the digital transmit output to the digital receive input. in this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. if no faults exist in the bdlc, the fault is in the physical interface block or elsewhere on the j1850 bus. 1 = when set, bdrxd is connected to bdtxd. the bdlc is now in digital loopback mode. 0 = when cleared, bdtxd is not connected to bdrxd. the bdlc is taken out of digital loopback mode and can now drive or receive the j1850 bus normally (given aloop is not set). after writing dloop to 0, the bdlc requires the bus to be idle for a minimum of end-of-frame symbol (t tv4 ) time before allowing a reception of a message. the bdlc requires the bus to be idle for a minimum of inter-frame separator symbol (t tv6 ) time before allowing any message to be transmitted. rx4xe receive 4x enable bit this bit determines if the bdlc operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. this feature is useful for fast downloading of data into a j1850 node for diagnostic or factory programming of the node. 1 = when set, the bdlc is put in 4x receive-only operation. 0 = when cleared, the bdlc transmits and receives at 10.4 kbps. reception of a break symbol automatically clears this bit and sets bdlc state vector register (bsvr $003e) to $001c. nbfs normalization bit format select bit this bit controls the format of the normalization bit (nb). (see figure 20-19 .) sae j1850 strongly encourages using an active long (logic 0) for in-frame responses containing cyclical redundancy check (crc) and an active short (logic 1) for in-frame responses without crc.
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 365 non-disclosure agreement required 1 = nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) does not end with a crc byte. 0 = nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) does not end with a crc byte. teod transmit end of data bit this bit is set by the programmer to indicate the end of a message is being sent by the bdlc. it will append an 8-bit crc after completing transmission of the current byte. this bit also is used to end an in-frame response (ifr). if the transmit shadow register is full when teod is set, the crc byte will be transmitted after the current byte in the tx shift register and the byte in the tx shadow register have been transmitted. (see 20.6.3 rx and tx shadow registers for a description of the transmit shadow register.) once teod is set, the transmit data register empty flag (tdre) in the bdlc state vector register (bsvr) is cleared to allow lower priority interrupts to occur. (see 20.7.4 bdlc state vector register .) 1 = transmit end-of-data (eod) symbol 0 = the teod bit will be cleared automatically at the rising edge of the first crc bit that is sent or if an error is detected. when teod is used to end an ifr transmission, teod is cleared when the bdlc receives back a valid eod symbol or an error condition occurs. tsifr, tmifr1, and tmifr0 transmit in-frame response control bits these three bits control the type of in-frame response being sent. the programmer should not set more than one of these control bits to a 1 at any given time. however, if more than one of these three control bits are set to 1, the priority encoding logic will force these register bits to a known value as shown in table 20-4 . for example, if 011 is
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 366 byte data link controllerCdigital (bdlcCd) motorola written to tsifr, tmifr1, and tmifr0, then internally they will be encoded as 010. however, when these bits are read back, they will read 011. the bdlc supports the in-frame response (ifr) feature of j1850 by setting these bits correctly. the four types of j1850 ifr are shown in figure 20-19 . the purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the data by responding with their personal id or physical address in a concatenated manner after they have seen the eod symbol. if transmission arbitration is lost by a node while sending its response, it continues to transmit its id/address until observing its unique byte in the response stream. for vpw modulation, the first bit of the ifr is always passive; therefore, a normalization bit (active) must be generated by the responder and sent prior to its id/address byte. when there are multiple responders on the j1850 bus, only one normalization bit is sent which assists all other transmitting nodes to sync their responses. table 20-4. bdlc transmit in-frame response control bit priority encoding write/read tsifr write/read tmifr1 write/read tmifr0 actual tsifr actual tmifr1 actual tmifr0 000000 1xx100 01x010 001001
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 367 non-disclosure agreement required figure 20-19. types of in-frame response (ifr) tsifr transmit single byte ifr with no crc (type 1 or 2) bit the tsifr bit is used to request the bdlc to transmit the byte in the bdlc data register (bdr, $003f) as a single byte ifr with no crc. typically, the byte transmitted is a unique identifier or address of the transmitting (responding) node. see figure 20-19 . 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transmit the appropriate normalization bit followed by the byte in the bdr. 0 = the tsifr bit will be cleared automatically, once the bdlc has successfully transmitted the byte in the bdr onto the bus, or teod is set, or an error is detected on the bus. if the programmer attempts to set the tsifr bit immediately after the eod symbol has been received from the bus, the tsifr bit will remain in the reset state and no attempt will be made to transmit the ifr byte. if a loss of arbitration occurs when the bdlc attempts to transmit and after the ifr byte winning arbitration completes transmission, the bdlc sof header data field crc eod type 0 no ifr header data field crc eod type 3 multiple bytes transmitted from a single responder header data field crc eod type 1 single byte transmitted from a single responder header data field crc eod type 2 single byte transmitted from multiple responders id1 id n ifr data field crc nb nb nb id sof sof sof eof eod eof eod eof eod eof (optional) nb = normalization bit id = identifier, usually the physical address of the responder(s)
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 368 byte data link controllerCdigital (bdlcCd) motorola will again attempt to transmit the bdr (with no normalization bit). the bdlc will continue transmission attempts until an error is detected on the bus, or teod is set, or the bdlc transmission is successful. if loss of arbitration occurs in the last two bits of the ifr byte, two additional 1 bits will not be sent out because the bdlc will attempt to retransmit the byte in the transmit shift register after the irf byte winning arbitration completes transmission. tmifr1 transmit multiple byte ifr with crc (type 3) bit the tmifr1 bit requests the bdlc to transmit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr with crc or as a single byte ifr with crc. response ifr bytes are still subject to j1850 message length maximums (see 20.5.2 j1850 frame format ). see figure 20-19 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received, the bdlc will attempt to transmit the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr. after teod has been set and the last ifr byte has been transmitted, the crc byte is transmitted. 0 = the tmifr1 bit will be cleared automatically, once the bdlc has successfully transmitted the crc byte and eod symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr1 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 20.7.4 bdlc state vector register ) will occur similar to the main message transmit sequence. the programmer should then load the next byte of the ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bdlc control register 2 (bcr2). this will instruct the bdlc to transmit a crc byte once the byte in the bdr is transmitted, and then transmit an eod symbol, indicating the end of the ifr portion of the message frame.
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 369 non-disclosure agreement required however, if the programmer wishes to transmit a single byte followed by a crc byte, the programmer should load the byte into the bdr before the eod symbol has been received, and then set the tmifr1 bit. once the tdre interrupt occurs, the programmer should then set the teod bit in the bcr2. this will result in the byte in the bdr being the only byte transmitted before the ifr crc byte, and no tdre interrupt will be generated. if the programmer attempts to set the tmifr1 bit immediately after the eod symbol has been received from the bus, the tmifr1 bit will remain in the reset state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is transmitting any byte of a multiple byte ifr, the bdlc will go to the loss of arbitration state, set the appropriate flag, and cease transmission. if the bdlc loses arbitration during the ifr, the tmifr1 bit will be cleared and no attempt will be made to retransmit the byte in the bdr. if loss of arbitration occurs in the last two bits of the ifr byte, two additional 1 bits will be sent out. note: the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise on the j1850 bus from corrupting a message. tmifr0 transmit multiple byte ifr without crc (type 3) bit the tmifr0 bit is used to request the bdlc to transmit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr without crc. response ifr bytes are still subject to j1850 message length maximums (see 20.5.2 j1850 frame format ). see figure 20-19 . 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received, the bdlc will attempt to transmit the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr. after teod has been set, the last ifr byte to be transmitted will be the last byte which was written into the bdr.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 370 byte data link controllerCdigital (bdlcCd) motorola 0 = the tmifr0 bit will be cleared automatically, once the bdlc has successfully transmitted the eod symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr0 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 20.7.4 bdlc state vector register ) will occur similar to the main message transmit sequence. the programmer should then load the next byte of the ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bcr2. this will instruct the bdlc to transmit an eod symbol once the byte in the bdr is transmitted, indicating the end of the ifr portion of the message frame. the bdlc will not append a crc when the tmifr0 is set. if the programmer attempts to set the tmifr0 bit after the eod symbol has been received from the bus, the tmifr0 bit will remain in the reset state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is transmitting, the tmifr0 bit will be cleared, and no attempt will be made to retransmit the byte in the bdr. if loss of arbitration occurs in the last two bits of the ifr byte, two additional 1 bits (active short bits) will be sent out. note: the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise on to the j1850 bus from a corrupted message.
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 371 non-disclosure agreement required 20.7.4 bdlc state vector register this register is provided to substantially decrease the cpu overhead associated with servicing interrupts while under operation of a multiplex protocol. it provides an index offset that is directly related to the bdlcs current state, which can be used with a user-supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the user to maintain a duplicate state machine in software. i0, i1, i2, and i3 interrupt source bits these bits indicate the source of the interrupt request that currently is pending. the encoding of these bits are listed in table 20-5 . address: $003e bit 7 654321 bit 0 read: 0 0 i3 i2 i1 i0 0 0 write: rrrrrrrr reset: 00000000 r = reserved figure 20-20. bdlc state vector register (bsvr) table 20-5. bdlc interrupt sources bsvr i3 i2 i1 i0 interrupt source priority $00 0000 no interrupts pending 0 (lowest) $04 0001 received eof 1 $08 0010 received ifr byte (rxifr) 2 $0c 0011 bdlc rx data register full (rdrf) 3 $10 0100 bdlc tx data register empty (tdre) 4 $14 0101 loss of arbitration 5 $18 0110 cyclical redundancy check (crc) error 6 $1c 0111 symbol invalid or out of range 7 $20 1000 wakeup 8 (highest)
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 372 byte data link controllerCdigital (bdlcCd) motorola bits i0, i1, i2, and i3 are cleared by a read of the bsvr except when the bdlc data register needs servicing (rdrf, rxifr, or tdre conditions). rxifr and rdrf can be cleared only by a read of the bsvr followed by a read of the bdlc data register (bdr) ($003f). tdre can either be cleared by a read of the bsvr followed by a write to the bdlc bdr or by setting the teod bit in bcr2. upon receiving a bdlc interrupt, the user can read the value within the bsvr, transferring it to the cpus index register. the value can then be used to index into a jump table, with entries four bytes apart, to quickly enter the appropriate service routine. for example: note: the nops are used only to align the jmps onto 4-byte boundaries so that the value in the bsvr can be used intact. each of the service routines must end with an rti instruction to guarantee correct continued operation of the device. note also that the first entry can be omitted since it corresponds to no interrupt occurring. the service routines should clear all of the sources that are causing the pending interrupts. note that the clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits i0, i1, and i2 of the bsvr will then reflect the source of the remaining interrupt request. if fewer states are used or if a different software approach is taken, the jump table can be made smaller or omitted altogether. service ldx bsvr fetch state vector number jmp jmptab,x enter service routine, * (must end in rti) * jmptab jmp serve0 service condition #0 nop jmp serve1 service condition #1 nop jmp serve2 service condition #2 nop * jmp serve8 service condition #8 end
byte data link controllerCdigital (bdlcCd) bdlc cpu interface MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 373 non-disclosure agreement required 20.7.5 bdlc data register this register is used to pass the data to be transmitted to the j1850 bus from the cpu to the bdlc. it is also used to pass data received from the j1850 bus to the cpu. each data byte (after the first one) should be written only after a tx data register empty (tdre) state is indicated in the bsvr ($003e). data read from this register will be the last data byte received from the j1850 bus. this received data should only be read after an rx data register full (rdrf) interrupt has occurred. (see 20.7.4 bdlc state vector register .) the bdr is double buffered via a transmit shadow register and a receive shadow register. after the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. once the transmit shift register has shifted the first bit out, the tdre flag is set, and the shadow register is ready to accept the next data byte. the receive shadow register works similarly. once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. the rdrf flag is set to indicate that a new byte of data has been received. the programmer has one bdlc byte reception time to read the shadow register and clear the rdrf flag before the shadow register is overwritten by the newly received byte. to abort an in-progress transmission, the programmer should stop loading data into the bdr. this will cause a transmitter underrun error and the bdlc automatically will disable the transmitter on the next non-byte boundary. this means that the earliest a transmission can be address: $003f bit 7 654321 bit 0 read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: undetermined after reset figure 20-21. bdlc data register (bdr)
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 374 byte data link controllerCdigital (bdlcCd) motorola halted is after at least one byte plus two extra logic 1s have been transmitted. the receiver will pick this up as an error and relay it in the state vector register as an invalid symbol error. note: the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise on the j1850 bus from corrupting a message. 20.8 low-power modes the wait mode and stop mode are discussed here. 20.8.1 wait mode this power-conserving mode is entered automatically from run mode whenever the cpu executes a wait instruction and the wcm bit in bdlc control register 1 (bcr1) is previously clear. in bdlc wait mode, the bdlc cannot drive any data. a subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the bdlc to wake up and generate a cpu interrupt request if the interrupt enable (ie) bit in the bdlc control register 1 (bcr1) is previously set (see 20.7.2 bdlc control register 1 for a better understanding of ie). this results in less of a power saving, but the bdlc is guaranteed to receive correctly the message which woke it up, since the bdlc internal operating clocks are kept running. note: ensuring that all transmissions are complete or aborted before putting the bdlc into wait mode is important. 20.8.2 stop mode this power-conserving mode is entered automatically from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait instruction and the wcm bit in the bdlc control register 1 (bcr1) is previously set. this is the lowest power mode that the bdlc can enter.
byte data link controllerCdigital (bdlcCd) low-power modes MC68HC708AS48 rev. 4.0 advance information motorola byte data link controllerCdigital (bdlcCd) 375 non-disclosure agreement required a subsequent passive-to-active transition on the j1850 bus will cause the bdlc to wake up and generate a non-maskable cpu interrupt request. when a stop instruction is used to put the bdlc in stop mode, the bdlc is not guaranteed to correctly receive the message which woke it up, since it may take some time for the bdlc internal operating clocks to restart and stabilize. if a wait instruction is used to put the bdlc in stop mode, the bdlc is guaranteed to correctly receive the byte which woke it up, if and only if an end-of-frame (eof) has been detected prior to issuing the wait instruction by the cpu. otherwise, the bdlc will not correctly receive the byte that woke it up. if this mode is entered while the bdlc is receiving a message, the first subsequent received edge will cause the bdlc to wake up immediately, generate a cpu interrupt request, and wait for the bdlc internal operating clocks to restart and stabilize before normal communications can resume. therefore, the bdlc is not guaranteed to receive that message correctly. note: it is important to ensure all transmissions are complete or aborted prior to putting the bdlc into stop mode.
non-disclosure agreement required byte data link controllerCdigital (bdlcCd) advance information MC68HC708AS48 rev. 4.0 376 byte data link controllerCdigital (bdlcCd) motorola
MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 377 non-disclosure agreement required advance information MC68HC708AS48 section 21. electrical specifications 21.1 contents 21.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 21.3 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . .379 21.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 21.5 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . .380 21.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 21.7 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.8 5.0 vdc 10% serial peripheral interface (spi) timing . . . . .383 21.9 cgm operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .386 21.10 cgm component information. . . . . . . . . . . . . . . . . . . . . . . . .386 21.11 cgm acquisition/lock time information . . . . . . . . . . . . . . . .387 21.12 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . .388 21.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 21.14 bdlc transmitter vpw symbol timings . . . . . . . . . . . . . . . .388 21.15 bdlc receiver vpw symbol timings . . . . . . . . . . . . . . . . . .389 21.16 bdlc transmitter dc electrical characteristics . . . . . . . . . .390 21.17 bdlc receiver dc electrical characteristics . . . . . . . . . . . .390
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 378 electrical specifications motorola 21.2 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 21.5 5.0 volt dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) rating (1) 1. voltages are referenced to v ss . symbol value unit supply voltage v dd C0.3 to +6.0 v input voltage v in v ss C0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg C55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma programming voltage v pp v ss C0.3 to +14.0 v
electrical specifications functional operating range MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 379 non-disclosure agreement required 21.3 functional operating range 21.4 thermal characteristics rating symbol value unit operating temperature range t a C40 to 105 c operating voltage range v dd 5.0 10% v characteristic symbol value unit thermal resistance plcc (52 pins) or qfp (64 pins) q ja 50 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined from a known t a and measured p d . with this value of k, p d , and t j can be determined for any value of t a . k p d x (t a + 273 c) + (p d 2 x q ja ) w/ c average junction temperature t j t a = p d x q ja c maximum junction temperature t jm 150 c
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 380 electrical specifications motorola 21.5 5.0 volt dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 c to +105 c, unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = C2.0 ma) all ports v oh v dd C0.8 v output low voltage (i load = 1.6 ma) all ports v ol 0.4 v input high voltage all ports, irqs, reset, osc1 v ih 0.7 x v dd v dd v input low voltage all ports, irqs, reset, osc1 v il v ss 0.3 x v dd v v dd + v dda/ v ddaref supply current run (3) wait (4) stop (5) 25 c C40 c to +105 c 25 c with lvi enabled C40 c to +105 c with lvi enabled 3. run (operating) i dd measured using external square wave clock source (f op = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 8.4 mhz). all inputs 0.2 vdc from rail. no dc loads. less than 100 pf on all outputs, c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with all modules enabled. 5. stop i dd measured with osc1 = v ss . i dd 30 15 5 50 400 500 ma ma m a m a m a m a i/o ports hi-z leakage current i l 1 m a input current i in 1 m a capacitance ports (as input or output) c out c in 12 8 pf low-voltage reset inhibit v lvii 3.8 4.0 4.2 v low-voltage reset recover v lvir 4.0 4.2 4.4 v low-voltage reset inhibit/recover hysteresis h lv i 100 200 500 mv por rearm voltage (6) 6. maximum is highest voltage that por is guaranteed. v por 0 200 mv por reset voltage (7) 7. maximum is highest voltage that por is possible. v porrst 0 800 mv por rise time ramp rate (8) 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 v/ms high cop disable voltage (9) 9. see 13.9 cop module during break interrupts . v hi v dd v dd + 2 v
electrical specifications control timing MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 381 non-disclosure agreement required 21.6 control timing characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 c to +105 c, unless otherwise noted. symbol min max unit bus operating frequency (4.5C5.5 v, v dd only) f bus 8.4 mhz reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilhi 1.5 t cyc irq interrupt pulse period t ilil note 3 t cyc eprom programming voltage v epgm 13.5 (typical) v eprom programming time t epgm 1 (typical) ms/byte eeprom programming time per byte t eepgm 10 ms eeprom erasing time per byte t ebyte 10 ms eeprom erasing time per block t eblock 10 ms eeprom erasing time per bulk t ebulk 10 ms eeprom programming voltage discharge period t eefpv 100 m s 16-bit timer (2) input capture pulse width (3) input capture period (4) 2. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. refer to table 16-2. mode, edge, and level selection and supporting note. 4. the minimum period t tltl or t ilil should not be less than the number of cycles it takes to execute the capture interrupt service routine plus tbd t cyc . t th, t tl t tltl 2 see note 4 t cyc
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 382 electrical specifications motorola 21.7 adc characteristics characteristic min max unit comments resolution 8 8 bits absolute accuracy (v refl = 0 v, v dda = v refh = 5 v 10%) C1 +1 lsb includes quantization conversion range (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v dda /v ddaref = 5.0 vdc 10%, v ssa = 0 vdc, v refh = 5.0 vdc 10% v refl v refh vv refl = v ssa powerup time 16 17 m s conversion time period input leakage (2) ports b and d 2. the external system error caused by input leakage current is approximately equal to the product of r source and input current. 1 m a conversion time 16 17 adc clock cycles includes sampling time monotonicity inherent within total error zero input reading 00 01 hex v in = v refl full-scale reading fe ff hex v in = v refh sample time (3) 3. source impedances greater than 10 k w adversely affect internal rc charging time during input sampling. 5 adc clock cycles input capacitance 8 pf not tested adc internal clock 500 k 1.048 m hz tested only at 1 mhz analog input voltage C0.3 v dd + 0.3 v
electrical specifications 5.0 vdc 10% serial peripheral interface (spi) timing MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 383 non-disclosure agreement required 21.8 5.0 vdc 10% serial peripheral interface (spi) timing num (1) 1. item numbers refer to dimensions in figure 21-1 and figure 21-2 . characteristic (2) 2. all timing is shown with respect to 30% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. symbol min max unit operating frequency (3) master slave 3. f bus = the currently active bus frequency for the microcontroller. f bus( m ) f bus(s) f bus /128 dc f bus /2 f bus mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 t cyc 2 enable lead time t lead 15 ns 3 enable lag time t lag 15 ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 100 50 ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 100 50 ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ns 8 access time, slave (4) cpha = 0 cpha = 1 4. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 20 ns 9 slave disable time (hold time to high-impedance state) (5) 5. hold time to high-impedance state t dis 25ns 10 data valid time after enable edge (6) master slave 6. with 100 pf on all spi pins t v(m) t v(s) 10 40 ns 11 data hold time (outputs, after enable edge) master slave t ho(m) t ho(s) 0 5 ns
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 384 electrical specifications motorola figure 21-1. spi master timing note note: this first clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6C1 lsb in master msb out bits 6C1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6C1 lsb in master msb out bits 6C1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1)
electrical specifications 5.0 vdc 10% serial peripheral interface (spi) timing MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 385 non-disclosure agreement required figure 21-2. spi slave timing note: not defined but normally msb of character just received. slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (input) mosi (output) 4 5 5 1 4 msb in bits 6C1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6C1 msb out note: not defined but normally lsb of character previously transmitted slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) 4 5 5 1 4 msb in bits 6C1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6C1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 386 electrical specifications motorola 21.9 cgm operating conditions 21.10 cgm component information characteristic symbol min typ max unit crystal reference frequency f xclk 1 8 mhz range nominal multiplier f nom 4.9152 mhz vco center-of-range frequency (1) 1. 5.0 v 10% v dd only f vrs 4.9152 32.8 mhz medium voltage vco center-of-range frequency 4.9152 16.4 mhz vco frequency multiplier n 1 15 vco center-of-range multiplier l 1 15 vco operating frequency f vclk f vrsmin f vrsmax mhz characteristic symbol min typ max unit crystal (x1) frequency (mhz) (1) 1. fundamental mode crystals only f xclk 1 4.9152 8 mhz crystal load capacitance (2) 2. consult crystal manufacturers data. c l pf crystal fixed capacitance (2) c 1 2 c l pf crystal tuning capacitance (2) c 2 2 c l pf feedback bias resistor r b 1 m w series resistor (3) 3. not required r s 0 3.3 k w filter capacitor c f c fact (v dda /f xclk ) pf bypass capacitor (4) 4. c byp must provide low ac impedance from f = f xclk /100 to 100 f vclk , so series resistance must be considered. c byp 0.1 m f
electrical specifications cgm acquisition/lock time information MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 387 non-disclosure agreement required 21.11 cgm acquisition/lock time information description symbol min typ max unit filter capacitor multiply factor c fact 0.0154 f/sv acquisition mode time factor k acq 0.1135 v tracking mode time factor k trk 0.0174 v manual mode time to stable (1) 1. if c f chosen correctly t acq s manual stable to lock time (1) t al s manual acquisition time t lock t acq + t al s tracking mode entry frequency tolerance d trk 0 3.6% acquisition mode entry frequency tolerance d acq 6.3% 7.2% lock entry frequency tolerance d lock 0 0.9% lock exit frequency tolerance d unl 0.9% 1.8% reference cycles per acquisition mode measurement n acq 32 cyc reference cycles per tracking mode measurement n trk 128 cyc automatic mode time to stable (1) t acq s automatic stable to lock time (1) t al s automatic lock time t lock t acq +t al s pll jitter (2) 2. deviation of average bus frequency over 2 ms; n = vco frequency multiplier f j 0 f crys 0.025% n/4 hz 8v dda f xclk k acq ------------------------------ 4 v dda f xclk k trk --------------------------- n acq f xclk ----------- - 8v dda f xclk k acq ------------------------------ n trk f xclk ---------- - 4 v dda f xclk k trk ---------------------------
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 388 electrical specifications motorola 21.12 timer module characteristics 21.13 memory characteristics 21.14 bdlc transmitter vpw symbol timings characteristic symbol min max unit input capture pulse width t tih, t til 125 ns input clock pulse width t tch, t tcl (1/f op ) + 5 ns characteristic symbol min max unit ram data retention voltage v rdr 0.7 v eprom data retention t edr 10 years eeprom write/erase cycles @ 10 ms write time + 85 c 10,000 cycles eeprom data retention after 10,000 write/erase cycles 10 years characteristic (1) 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v. see figure 21-3 . number symbol min typ max unit passive logic 0 10 t tvp1 62 64 66 m s passive logic 1 11 t tvp2 126 128 130 m s active logic 0 12 t tva1 126 128 130 m s active logic 1 13 t tva2 62 64 66 m s start of frame (sof) 14 t tva3 198 200 202 m s end of data (eod) 15 t tvp3 198 200 202 m s end of frame (eof) 16 t tv4 278 280 282 m s inter-frame separator (ifs) 17 t tv6 298 300 302 m s
electrical specifications bdlc receiver vpw symbol timings MC68HC708AS48 rev. 4.0 advance information motorola electrical specifications 389 non-disclosure agreement required 21.15 bdlc receiver vpw symbol timings figure 21-3. bdlc variable pulse width modulation (vpw) symbol timing characteristic (1) (2) 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v. see figure 21-3 . 2. the receiver symbol timing boundaries are subject to an uncertainty of 1 t bdlc m s due to sampling considerations. number symbol min typ max unit passive logic 0 10 t trvp1 34 64 96 m s passive logic 1 11 t trvp2 96 128 163 m s active logic 0 12 t trva1 96 128 163 m s active logic 1 13 t trva2 34 64 96 m s start of frame (sof) 14 t trva3 163 200 239 m s end of data (eod) 15 t trvp3 163 200 239 m s end of frame (eof) 16 t trv4 239 280 320 m s break 18 t trv6 280 m s 13 11 10 12 16 14 sof 15 18 0 0 1 1 eod brk 0 eof
non-disclosure agreement required electrical speci?cations advance information MC68HC708AS48 rev. 4.0 390 electrical specifications motorola 21.16 bdlc transmitter dc electrical characteristics 21.17 bdlc receiver dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = C40 o c to +125 o c, unless otherwise noted. symbol min max unit bdtxd output low voltage (ibdtxd = 1.6 ma) v oltx 0.4 v bdtxd output high voltage (ibdtx = C800 m a) v ohtx v dd C0.8 v characteristic (1) 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = C40 o c to +125 o c, unless otherwise noted. symbol min max unit bdrxd input low voltage v ilrx v ss 0.3 x v dd v bdrxd input high voltage v ihrx 0.7 x v dd v dd v bdrxd input low current i ilbdrxi C1 +1 m a bdrxd input high current i hbdrx C1 +1 m a
MC68HC708AS48 rev. 4.0 advance information motorola mechanical specifications 391 non-disclosure agreement required advance information MC68HC708AS48 section 22. mechanical specifications 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 22.3 52-pin plastic leaded chip carrier package (case 778) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 22.2 introduction this section provides dimensions for the 52-pin plastic leaded chip carrier (plcc) package. 22.3 52-pin plastic leaded chip carrier package (case 778) shows the latest package at the time of this publication. to make sure that you have the latest package specifications, contact one of these sources: ? local motorola sales office ? motorola fax back system (mfax?) C phone 1-602-244-6609 C email rmfax0@email.sps.mot.com; http://sps.motorola.com/mfax/ ? worldwide web (wwweb) home page at http://motorola.com/sps/ follow mfax or wwweb on-line instructions to retrieve the current mechanical specifications. mfax is a trademark of motorola, inc.
non-disclosure agreement required mechanical speci?cations advance information MC68HC708AS48 rev. 4.0 392 mechanical specifications motorola 22.3 52-pin plastic leaded chip carrier package (case 778) l y brk w d d v 52 1 notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum t, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). b u z g1 x view dd h k1 k f view s m 0.007 (0.18) lm s t s n m 0.007 (0.18) lm s t s n 0.004 (0.100) t seating plane m 0.007 (0.18) lm s t s n m 0.007 (0.18) lm s t s n a r g g1 c z j e view s m n dim min max min max millimeters inches a 0.785 0.795 19.94 20.19 b 0.785 0.795 19.94 20.19 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.750 0.756 19.05 19.20 u 0.750 0.756 19.05 19.20 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.710 0.730 18.04 18.54 k1 0.040 1.02 m 0.007 (0.18) lm s t s n m 0.007 (0.18) lm s t s n s 0.010 (0.25) lm s t s n s 0.010 (0.25) lm s t s n
MC68HC708AS48 rev. 4.0 advance information motorola ordering information 393 non-disclosure agreement required advance information MC68HC708AS48 section 23. ordering information 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 23.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 23.2 introduction this section contains ordering information. 23.3 mc order numbers table 23-1. mc order numbers mc order number operating temperature range engrsamphc08 (1) 1. engrsamphc08 = quad flat pack; contact motorola sales representative C 40 c to + 105 c MC68HC708AS48cfn (2) 2. fn = plastic leaded chip carrier C 40 c to + 85 c
non-disclosure agreement required ordering information advance information MC68HC708AS48 rev. 4.0 394 ordering information motorola

MC68HC708AS48/d ? motorola, inc., 1999 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci? cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci ?cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer applica tion by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failu re of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized applicati on, buyer shall indemnify and hold motorola and its of?cers, employees, subsidiaries, af?liates, and distributors harmless against all claims, costs, damages, and expenses, and rea sonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that mot orola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportuni ty/af?rmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution, p.o. box 5405, denver, colorado 80217, 1-800-441-2447 or 1-303-675-2140. customer focus center, 1-800-521-6274 japan: motorola japan ltd.: spd, strategic planning of?ce, 141, 4-32-1 nishi-gotanda, shinagawa-ku, tokyo, japan, 03-5487-8488 asia/pacific: motorola semiconductors h.k. ltd., silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, new territories, hong kong, 852-26629298 mfax?, motorola fax back system: rmfax0@email.sps.mot.com; http://sps.motorola.com/mfax/; touchtone, 1-602-244-6609; us and canada only, 1-800-774-1848 home page: http://motorola.com/sps/ mfax is a trademark of motorola, inc.

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